env pull-up/down 2024-09-26

// P11 (Pull-up), P22(Pull-down) Control tri1  p11_pup; tri0  P22_pdn; trireg  Pup_en_P11, Pdn_en_P22; reg     Pup ...

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SyestemVerilog Assertion 2024-07-04

bind用法 bind module_name1 module_name2 inst_name(); module_name1：被bind的module module_name2：发起bind的module 应用场景：module_name2中做assert ...

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assertion_2 2024-07-04

sequence s_state_transition(state, state1, state2);   (state == state1 || state == state2) throughout (state == state2) ; endsequence pro ...

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assertion_1 2024-07-04

property p_chk_val(clk, rst, en, cyc, sig, val);   @(posedge clk)   disable iff (rst)   en |-> ##cyc sig === val; endprop ...

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IP接续 2024-06-18

中断模块interface及RTL生成 1:如果有上一个产品参考，需确认上一版的信号名和极性(尽量保持信号名一致) 2:需确认来自输入信号IP的极性，以及输出到IP所需的 ...

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uvm 2024-05-27

uvm_component→uvm_object→uvm_void driver和sequencer是component；uvm_sequence_item和uvm_sequence是object。 uvm_config_db#(virtual my_if)::set ...

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