日志
env pull-up/down
| |
// P11 (Pull-up), P22(Pull-down) Control
tri1 p11_pup;
tri0 P22_pdn;
trireg Pup_en_P11, Pdn_en_P22;
reg Pup_en_P11_reg, Pdn_en_P22_reg;
assign Pup_en_P11 = Pup_en_P11_reg;
assign Pdn_en_P22 = Pdn_en_P22_reg;
tranif1( P11, P11_pup, Pup_en_P11);
tranif1( P22, P22_pdn, Pdn_en_P22);
initial begin
Pup_en_P11_reg = 1'b1; // P11 is pull-up
Pdn_en_P22_reg = 1'b1; // P22 is pull-dwon
#10 // Wait 10 cycle
Pup_en_P11_reg = 1'bz;
end
全部作者的其他最新日志
- • SyestemVerilog Assertion
- • assertion_2
- • assertion_1
- • IP接续
- • uvm
/2 
eetop公众号
创芯大讲堂
创芯人才网