難，然而世界先進國家的各大IC廠商在ESD防護上的研究

更趨熱烈，各式各樣的技術都被嘗試用在ESD防護上，因

而已有六百多件ESD相關的美國專利已刊登出來。本文乃

就各種可能的技術中，介紹在CMOS製程技術下較實用可

行的ESD防護設計給IC相關設計者一個概念，但是在產品

商業化時，要注意專利的智慧財產權問題。大多數的ESD

設計都已有專利或者專利申請中，因其實在是高難度的設

計工作。

　　ESD的防護設計除了本文所談的技術之外，另外要注

意整顆積體電路的ESD防護架構。ESD的防護是整顆積體

電路的問題，而不只是Input PAD，Output PAD，或 Power

PAD的問題，即使各個PAD都有很好的ESD防護能力，不

見得整顆積體電路就有很高的ESD防護能力。採用適當的

全晶片(whole-chip)防護架構設計，才能真正提昇整顆積體

電路的ESD防護能力，並且可以節省I/O PAD上ESD防護元

件的尺寸與佈局面積。全晶片ESD防護架構已經是目前各

大公司專利競逐的焦點所在，對此技術未有警覺性的公司

要特別注意這項技術的發展。

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