## 精读笔记 - <低压触发SCR结构用于片上ESD防护的输出和输入Pads>

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A low-voltage triggering SCR for on-chip ESD protection at output and input pads

摘要：

A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V.<>

所用工艺：<工艺>

0.8um CMOS Process

器件剖面：<剖面>

TLP测试数据：<测试数据图表>

从Fig. 3可以看出，嵌入mos栅极的长度L=0.8um时，LVTSCR 的BV是小于L=1um时LVTSCR和NMOS的BV的。MOS源漏穿通电压<MOS源衬的穿通电压，而且MOS的源漏穿通电压还可以根据栅极长度来进行调节。

Fig. 4这种测试数据我还是第一次见，一般见到的都是TLP测试数据，但是这篇文章中未出现TLP测试数据。TLP测试设备在1985年由Maloney和Khuranal引入，可能当时TLP测试还岌岌无名，未成为ESD研究领域的及其重要的测试之一吧！

文章结论与创新点：<自拟>

将触发器件（NMOS）集成到主器件中（SCR）。构造出经典的LVTSCR结构

我的评论及想法：<评论及想法>

如何使用LVTSCR对input端口进行ESD保护进行了说明：Anode连接到PAD，Cathode连接到GND bus。输入晶体管的栅极连接到LVTSCR的“drain tap”（也就是嵌入NMOS的漏极，嵌入NMOS的源极是和阴极接在一起的）

文章中给出了这样连接形成保护的原因。

“The potential of the drain tap cannot exceed the Vtrig of the LVTSCR, which is equivalent to BVdss of the nMOS. The gate oxide breakdown voltage is typically much greater than BVdss. Thus the LVTSCR alone protects the gate oxides.” (Chatterjee 和 Polgreen, 1991, p. 22)

但是目前随着工艺越来越先进，栅氧化层正在变的越来越薄，栅氧的击穿电压变得比源漏的穿通电压要小。所以文章的“The gate oxide breakdown voltage is typically much greater than BVdss ”在先进工艺下已经反过来了。文中提出这种保护电路的接法也不适用于先进工艺了。

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日期：2025-01-21