##精读笔记-<电源轨ESD电路的仿真与验证>

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Power rail ESD circuit simulation and verification

摘要：

In order to advance the performance of the ESD circuit for the power rail protection, a kind of design scheme named GDNMOS (Qate ~riven NMOS) is studied in this paper. NMOS, inverter and RC couple cell are the makeup in this scheme. Device simulation in a pre_Si phase will be an economical way. NMOS parameters are optimized in a device simulation way firstly. By discharge time study the RC-time is ascertained to differentiate ESD or not. And short delay is achieved by appropriate inverter design. This scheme with optimized parameters, not only the tum on speed is accelerated, but also better transparency is achieved. Tum on uniformity of the NMOS is also enhanced by this scheme. The design is verified in a O.18um salicided CMOS process fmally.

所用工艺：<工艺>

0.18 um Salicided CMOS Process

器件剖面：<剖面>

TLP测试数据：<测试数据图表>

文章对于该结构的设计过程讲的还是蛮清楚的，如果没有设计过相关结构，可以作为一个不错的参考。

文章结论与创新点：<自拟>

本文提出了一种设计功率钳位电路GDNMOS的有效方法。为了优化NMOS器件参数，进行了器件级仿真。并进行了电路级仿真，以达到最佳性能。该设计最终在0.18 um的盐化CMOS工艺下得到验证。通过TLP测试，GDNMOS的失效电流为4.5 A。在HBM中，热击穿电压约为6750V.

我的评论及想法：<评论及想法>

奇怪的是，作者设计的这个RC加反向器件触发BigFET的结构居然是有回滞的，证明后面那个MOSFET内部寄生的NPN开启了，并没有完全使用沟道进行泄放电流。

很奇怪不应该这样的，难道是RC常熟设置的不合理吗？还是后面BigFET的总宽度设计的太窄了？

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日期：2025-01-15