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1. Compliant with the Interlaken Protocol Definition, Rev 1.2
2. 64/67 encoding and decoding3. Automatic word alignment
4. Self-synchronizing data scrambler
5. CRC32 generation and checking for lane data integrity
6. Serdes Interface 32bits
1. RTL verilog source code completed
2. Verification completed
3. FPGA synthesis, place and route completed
4. Document completed
Email: hpiclab@sina.com