Specification

1.       Compliant with the Interlaken Protocol Definition, Rev 1.2.

2.       Support for up to 10 Gbps serial data rate. SERDES interface width 10/16/20/32/40 option.

3.       Configurable internal data bus width of 64, 128, 256 or 512 bits.

4.       In-Band flow control and out of band flow control option, up to 256 channels.

5.       Data striping and de-striping across 1 to 24 lanes.

6.       Programmable BurstMax, BurstMin, BurstShort and MetaFrameSize parameters.

7.       64/67 encoding and decoding.

8.       Automatic word and lane alignment.

9.       Self-synchronizing data scrambler.

10.    CRC24 generation and checking for burst data integrity.

11.    CRC32 generation and checking for lane data integrity.

12.    Error checking and recovery.

13.   Technology independent. Can be targeted to different FPGAs and asics.

Status

1.      RTL verilog source code completed

2.      Verification completed

3.    FPGA synthesis, place and route completed

4.    Document completed

Contact

Email: hpiclab@sina.com