日志

Interlaken MAC 512bits

已有 967 次阅读| 2010-10-27 15:58 |个人分类:参考设计

Specification

1.     Compliant with the Interlaken Protocol Definition, Rev 1.2
2.   Internal data bus width of 512bits
3.   In-Band flow control, up to 256 channels
4.   Data striping and de-striping across 24 lanes
5.   Programmable BurstMax, BurstShort, BurstMin parameters
6.   Automatic lane alignment
7. CRC24 generation and checking for burst data integrity
8. Error checking and recovery

Status

1.      RTL verilog source code completed

2.        Verification completed
3.    FPGA synthesis, place and route completed
       4.    Document completed