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1. Hamming codes generation and checker with optional SECDED
a) Configurable code length n and message length k Matlab script
b) Data width configurable
c) verilog format output for easy integration with default systematic form
2. Easily pipelined to improve performance
1. RTL verilog source code completed
2. Verification completed
3. FPGA synthesis, place and route completed
4. Document completed
Email: hpiclab@sina.com