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1. Compliant with the Interlaken Protocol Definition, Rev 1.2
2. Internal data bus width of 64bits
3. In-Band flow control, up to 256 channels
4. Data striping and de-striping across 2 lanes
5. Programmable BurstMax, BurstShort, BurstMin parameters
6. Automatic lane alignment
7. CRC24 generation and checking for burst data integrity
8. Error checking and recovery
1. RTL verilog source code completed
2. Verification completed
3. FPGA synthesis, place and route completed
4. Document completed
Email:hpiclab@sina.com