日志
Ultra high speed parallel CRC generator/checker
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Specification
1. Parallel CRC generation and checker.
a) Configurable Matlab script.
b) Generator polynomial configurable.
c) Parallel data width configurable.
d) verilog format output for easy integration.
2. Ultra high speed (40G, 100G, 200G…) parallel CRC generation and checker.
Status
1. RTL verilog source code completed
2. Verification completed
3. FPGA synthesis, place and route completed
4. Document completed
Contact
Email: hpiclab@sina.com
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