终于出现了一个successful，可以小激动一下了。可话说回来，这只是基础的一小步。上图中可以看出一些信息，如一共有6个schematic转换成了verilog Netlist，但是还有两个p33和n33的管子，这个怎么个情况呢？

 

要办事先摸路，将产生的网表拿出来看一看。在brasilia目录下键入ls命令，会看到多了一个twobitadder.run1这个目录，不难从前面的操作中发现，这个目录就是刚刚运行全部的操作的工作目录。进入该目录中的ihnl子目录，我们刚才产生的网表文件分布在这个子目录下的cds0~cds5目录中，接下来见证奇迹的时刻，运行命令：cat cds*/netlist > twobitaddr.v

 

如此就能得到完整的网表文件了，至于cat这个非常有用的命令式什么意思，请百度it！这里，将生成的网表拿出来分析一下：

 

layout-grid-align: none" class=MsoNormal align=left>// Library - bcdee_sc, Cell - RS_XOR2_A, View - schematic

// LAST TIME SAVED: Jul  2 09:43:03 2014

// NETLIST TIME: Aug  9 20:10:38 2014

`timescale 1ns / 1ns

 

module RS_XOR2_A ( O, I1, I2 );

output  O;

 

input  I1, I2;

 

 

specify

    specparam CDS_LIBNAME  = "bcdee_sc";

    specparam CDS_CELLNAME = "RS_XOR2_A";

    specparam CDS_VIEWNAME = "schematic";

endspecify

 

p33  m12 ( .D(O), .B(cds_globals.vcc_), .G(net46),

     .S(cds_globals.vcc_));

p33  m10 ( .D(net18), .B(cds_globals.vcc_), .G(cdsNet0), .S(net46));

p33  m9 ( .D(net26), .B(cds_globals.vcc_), .G(I2), .S(net46));

p33  m4 ( .D(cds_globals.vss_), .B(cds_globals.vss_), .G(net26),

     .S(net18));

p33  m11 ( .D(net18), .B(cds_globals.vcc_), .G(net26),

     .S(cds_globals.vcc_));

p33  m1 ( .D(cds_globals.vss_), .B(cds_globals.vss_), .G(I1),

     .S(net26));

p33  m7 ( .D(net26), .B(cds_globals.vcc_), .G(I1),

     .S(cds_globals.vcc_));

p33  m6 ( .D(cdsNet0), .B(cds_globals.vcc_), .G(I2),

     .S(cds_globals.vcc_));

n33  m5 ( .D(O), .B(cds_globals.vss_), .G(net46),

     .S(cds_globals.vss_));

n33  m3 ( .D(net18), .B(cds_globals.vss_), .G(I2), .S(net46));

n33  m2 ( .D(net26), .B(cds_globals.vss_), .G(cdsNet0), .S(net46));

n33  m0 ( .D(cdsNet0), .B(cds_globals.vss_), .G(I2),

     .S(cds_globals.vss_));

 

endmodule

// Library - bcdee_sc, Cell - RS_INV_A, View - schematic

// LAST TIME SAVED: Jul  2 08:55:40 2014

// NETLIST TIME: Aug  9 20:10:38 2014

`timescale 1ns / 1ns

 

module RS_INV_A ( O, I );

output  O;

 

input  I;

 

 

specify

    specparam CDS_LIBNAME  = "bcdee_sc";

    specparam CDS_CELLNAME = "RS_INV_A";

    specparam CDS_VIEWNAME = "schematic";

endspecify

 

p33  m1 ( .D(O), .B(cds_globals.vcc_), .G(I), .S(cds_globals.vcc_));

n33  m0 ( .D(O), .B(cds_globals.vss_), .G(I), .S(cds_globals.vss_));

 

endmodule

// Library - bcdee_sc, Cell - RS_NR2_A, View - schematic

// LAST TIME SAVED: Jul  2 08:51:46 2014

// NETLIST TIME: Aug  9 20:10:38 2014

`timescale 1ns / 1ns

 

module RS_NR2_A ( O, I1, I2 );

output  O;

 

input  I1, I2;

 

 

specify

    specparam CDS_LIBNAME  = "bcdee_sc";

    specparam CDS_CELLNAME = "RS_NR2_A";

    specparam CDS_VIEWNAME = "schematic";

endspecify

 

p33  m3 ( .D(O), .B(cds_globals.vcc_), .G(I2), .S(net11));

p33  m2 ( .D(net11), .B(cds_globals.vcc_), .G(I1),

     .S(cds_globals.vcc_));

n33  m1 ( .D(O), .B(cds_globals.vss_), .G(I2), .S(cds_globals.vss_));

n33  m0 ( .D(O), .B(cds_globals.vss_), .G(I1), .S(cds_globals.vss_));

 

endmodule

// Library - bcdee_sc, Cell - RS_ND2_A, View - schematic

// LAST TIME SAVED: Jul  2 08:40:16 2014

// NETLIST TIME: Aug  9 20:10:38 2014

`timescale 1ns / 1ns

 

module RS_ND2_A ( O, I1, I2 );

output  O;

 

input  I1, I2;

 

 

specify

    specparam CDS_LIBNAME  = "bcdee_sc";

    specparam CDS_CELLNAME = "RS_ND2_A";

    specparam CDS_VIEWNAME = "schematic";

endspecify

 

p33  m3 ( .D(O), .B(cds_globals.vcc_), .G(I2), .S(cds_globals.vcc_));

p33  m2 ( .D(O), .B(cds_globals.vcc_), .G(I1), .S(cds_globals.vcc_));

n33  m1 ( .D(net16), .B(cds_globals.vss_), .G(I1),

     .S(cds_globals.vss_));

n33  m0 ( .D(O), .B(cds_globals.vss_), .G(I2), .S(net16));

 

endmodule

// Library - adder, Cell - fulladder, View - schematic

// LAST TIME SAVED: Aug  9 19:32:32 2014

// NETLIST TIME: Aug  9 20:10:38 2014

`timescale 1ns / 1ns

 

module fulladder ( Cout, Sum, A, B, Cin );

output  Cout, Sum;

 

input  A, B, Cin;

 

 

specify

    specparam CDS_LIBNAME  = "adder";

    specparam CDS_CELLNAME = "fulladder";

    specparam CDS_VIEWNAME = "schematic";

endspecify

 

RS_XOR2_A I6 ( .O(Sum), .I1(net9), .I2(Cin));

RS_XOR2_A I5 ( .O(net9), .I1(A), .I2(B));

RS_INV_A I4 ( .O(net12), .I(net14));

RS_NR2_A I3 ( .O(net14), .I1(A), .I2(B));

RS_ND2_A I2 ( .O(net20), .I1(net12), .I2(Cin));

RS_ND2_A I1 ( .O(Cout), .I1(net23), .I2(net20));

RS_ND2_A I0 ( .O(net23), .I1(A), .I2(B));

 

endmodule

// Library - adder, Cell - twobitadder, View - schematic

// LAST TIME SAVED: Aug  9 20:01:39 2014

// NETLIST TIME: Aug  9 20:10:38 2014

`timescale 1ns / 1ns

 

module twobitadder ( Cout, Sum, A, B, Cin );

 

output  Cout;

 

input  Cin;

 

output [1:0]  Sum;

 

input [1:0]  A;

input [1:0]  B;

 

 

specify

    specparam CDS_LIBNAME  = "adder";

    specparam CDS_CELLNAME = "twobitadder";

    specparam CDS_VIEWNAME = "schematic";

endspecify