日志
- 分享 tcl
- ! http://wiki.tcl.tk/1241 set fd7 ;# Results in stdout AND stderr being readable via fd7 文件: tcl exec reads stdout first then stderr - Stack Overflow.zip
- 分享 modelsim and debussy(verdi) run together
- the information should read from INSTALL/doc/linking(linking_dumping).pdf the pdf said : The Novas object file for FSDB dumping supports signal dumping in pure Verilog designs with ModelSim. but the otherresources(see below) said VHDL is also supported. http://blog ...
- 分享 the jitter lecture from pericomm
- the jitter lecture from pericomm the total jitter the random jitter the
- 分享 output the file using tcl
- puts " "
- 分享 the digital logic design
- counter to generate desired waveform pulse generation : the only conditions and else reset NOTE: else reset the only conditions not true again. shifter register ram r/w fsm these style. should be familiar
- 分享 tcl one point
- Tcl is also useful as a scripting language to tie other packages or programs together.
- 分享 tcl one point
- Tcl is also useful as a scripting language to tie other packages or programs together.
- 分享 file usage in verification
- the methodology $fscanf(para_file,"%s %h", token, value); case(token) parameter_name: para = value;
- 分享 debussy usage
- 1. modelsim.ini set the novas 2.vsim -c -do novas.novas
- 分享 file access
- while { ] = 0 } { incr number; if(res 0 ){ continue } puts "line$number:\"$line\""; }
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