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nonesense| fpga| tcl| hw|

分享 tcl: testset 2011-2-22 14:09; ! http://wiki.tcl.tk/1241 set fd7 ;# Results in stdout AND stderr being readable via fd7 文件: tcl exec reads stdout first then stderr - Stack Overflow.zip; 560 次阅读|0 个评论

分享 modelsim and debussy(verdi) run together: testset 2010-12-20 16:58; the information should read from INSTALL/doc/linking(linking_dumping).pdf the pdf said : The Novas object file for FSDB dumping supports signal dumping in pure Verilog designs with ModelSim. but the otherresources(see below) said VHDL is also supported. http://blog ...; 个人分类: fpga|3137 次阅读|0 个评论

分享 the jitter lecture from pericomm: testset 2010-12-13 10:06; the jitter lecture from pericomm the total jitter the random jitter the; 个人分类: hw|787 次阅读|0 个评论

分享 output the file using tcl: testset 2010-12-6 14:48; puts " "; 个人分类: tcl|676 次阅读|0 个评论

分享 the digital logic design: testset 2010-12-6 09:22; counter to generate desired waveform pulse generation : the only conditions and else reset NOTE: else reset the only conditions not true again. shifter register ram r/w fsm these style. should be familiar; 个人分类: fpga|500 次阅读|0 个评论

分享 tcl one point: testset 2010-12-3 10:32; Tcl is also useful as a scripting language to tie other packages or programs together.; 个人分类: tcl|487 次阅读|0 个评论

分享 tcl one point: testset 2010-12-3 10:32; Tcl is also useful as a scripting language to tie other packages or programs together.; 个人分类: tcl|295 次阅读|0 个评论

分享 file usage in verification: testset 2010-12-2 09:29; the methodology $fscanf(para_file,"%s %h", token, value); case(token) parameter_name: para = value;; 个人分类: fpga|394 次阅读|0 个评论

分享 debussy usage: testset 2010-11-26 15:40; 1. modelsim.ini set the novas 2.vsim -c -do novas.novas; 个人分类: fpga|440 次阅读|0 个评论

分享 file access: testset 2010-11-24 17:26; while { ] = 0 } { incr number; if(res 0 ){ continue } puts "line$number:\"$line\""; }; 个人分类: tcl|789 次阅读|0 个评论

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