日志
是时候学习SystemVerilog了 zz
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是时候学习SystemVerilog了
May 25, 2006 SystemVerilog Gains A Foothold In Verification
08/24/2007 Accellera Approves Functional Design Verification Standard
Synopsys and VMM
Feb 16, 2004 Arm and Synopsys to Deliver Industry's First Reference Verification Methodology Based on SystemVerilog
Sep 21, 2005 Synopsys Announces Source-Code License for SystemVerilog Verification Library
Mar 20, 2006 Synopsys Delivers First Complete SystemVerilog Design and Verification Flow
Jul 18, 2006 Industry Momentum Builds for the ARM-Synopsys VMM for SystemVerilog
Jul 26, 2006 Synopsys Donates Library of Advanced SystemVerilog Assertion Checkers to Accellera Standards Organization
Mar 5, 2007 Synopsys Extends VMM Methodology for Higher Functional Verification Productivity
May 14, 2007 Leading Semiconductor Companies in China Adopt the VMM Verification Methodology
2007-5-15 《SystemVerilog验证方法学》中文版首发式
Jun 5, 2007 Synopsys Launches VMM Catalyst Program With More Than 50 Member Companies
Advanced Verification Methodology (AVM) Cookbook for SystemVerilog and SystemC
March 30, 2005 Mentor Graphics Donation of SystemVerilog Assertion Version of Open Verification Library Accepted by Accellera
May 8, 2006 Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem
09 May 2006 Mentor Unveils Next Generation Verification Solution
May 31, 2007 Denali and Mentor Team to Enable Verification IP for SystemVerilog Verification Environments
Cadence and uRM/UVM
THE UNIFIED VERIFICATION METHODOLOGY
Incisive Plan-to-closure Methodology
Cadence and
August 16, 2007 Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology
August 16, 2007 Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology
20 Aug 2007 CADENCE与MENTOR GRAPHICS通过开放的SYSTEMVERILOG验证方法学实现协作
What others are saying
Faster verification is the goal at ST
Strange Bedfellows - Cadence, Mentor, and the OVM
SystemVerilog Methodologies – It’s Getting Wild
学习资料：
http://www.eda.org/sv/SystemVerilog_3.1a.pdf
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