//source the fsm_moore.tcl and print the process to terminal compile.log redirect -tee -file ${WORK_PATH}/compile.log {source -echo -verbose fsm_moore.tcl} //把{source -echo -verbose fsm_moore.tcl}脚本执行的结果放在compile.log
//step 1: read elaborate the RTL file list set TOP_MODULE top analze -format verilog elaborate$TOP_MODULE -architecture verilog current_desin $TOP_MODULE if { ==0}{ echo "link with error!"; exit; }; if { ==0}{ echo "check design with error!"; exit; }; //ste ...