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综合脚本-fsm_moore.tcl

热度 1已有 1811 次阅读| 2018-8-20 17:47 |个人分类:代码带回家|系统分类:芯片设计

//step 1: read & elaborate the RTL file list

set TOP_MODULE top
analze -format verilog [list fsm_moore.v top.v counter.v]
elaborate $TOP_MODULE -architecture verilog
current_desin $TOP_MODULE

if {[link] ==0}{
echo "link with error!";
exit;
};
if {[check_design] ==0}{
echo "check design with error!";
exit;
};

//step 2 :reset design first

reset_design

//step 3:write the unmapped ddc file

uniquify
set uniquify_naming_style. "%s_%d"
write -f ddc -hierachy -output ${UNMAPPED_PATH}/{TOP_MODULE}.ddc

// step 4 :define clock
set  CLK_NAME  clk_i
set  CLk_PERIOD  10
set  CLk_SKEW  [expr $CLk_PERIOD*0.05]
set  CLk_TRAN  [expr $CLk_PERIOD*0.01]
set  CLk_SRC_LATENCY [expr $CLk_PERIOD*0.1]
set  CLk_LATENCY  [expr $CLk_PERIOD*0.1]

create_clock   -period $CLk_PERIOD  [get_ports $CLK_NAME]
set_ideal_network  [get_ports $CLK_NAME]
set_dont_touch_network [get_ports $CLK_NAME]
set_drive 0   [get_ports $CLK_NAME]   //驱动能力无穷大
set_clock_uncertainty -setup $CLK_SKEW [get_clocks $CLK_NAME]
set_clock_transition -max $CLK_tran [get_clocks $CLK_NAME]
set_clock_latency  -source -max $CLK_SRC_LATENCY [get_clocks $CLK_NAME] //PCB板子引脚到芯片延迟
set_clock_latency  -max $CLK_SRC_LATENCY   [get_clocks $CLK_NAME] //芯片引脚到触发器延迟

//step 5 :set reset
set  RST_NAME   rst_l_i
set_ideal_network  [get_ports $RST_NAME]
set_dont_touch_network [get_ports $RST_NAME]
set drive 0   [get_ports $RST_NAME]

// set input delay(using timing budget)
set LIB_NAME   scx_csn_18ic_ss_125c
set WRITE_LOAD_MODEL csm18_wll0
set DRIVE_CELL   INVX1
set DRIVE_PIN   Y
set OPERA_CONDITIONAL ss_1p62v_125c
set ALL_IN_EXCEPT_CLK [remove_from_collection [all_inputs][get_ports $CLK_NAME]]
set INPUT_DELAY   [expr $CLk_PERIOD*0.6]
set_input_delay  $INPUT_DELAY -clock $CLK_NAME $ALL_IN_EXCEPT_CLK
set_drving_cell -lib_cell $(DRIVE_CELL) -pin ${DRIVE_PIN} $ALL_IN_EXCEPT_CLK

//set output delay
set OUTPUT_DELAY [expr $CLk_PERIOD*0.6]
set MAX_LOAD  [expr [load of $LIB_NAME/INVX8/A]*10]
set_output_delay $OUTPUT_DELAY -clock $CLK_NAME [all_outputs]
set_load   [expr $MAX_LOAD*3] [all_outputs]
set_isolate_ports -type buffer   [all_outputs]

//set max delay for comb logic
set_input_delay [expr $CLk_PERIOD*0.1] -clock $CLK_NAME -add_delay [get_ports a_i]
set_output_delay [expr CLk_PERIOD*0.1] -clock $CLK_NAME -add_dealy [get_ports y_o]

//set operating condition &write load model

set_operating_conditions -max $OPERA_CONDITION \
-max_library $LIB_NAME
set auto_wire_load_selection false