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Program 是Systemverilog引入的一种类似module的结构,它与module的区别如下:
program只能用于testbench,是不可综合的
program可以在module中,但是module不能在program中,也就是program只能在叶节点
program不可以包含always语句,只能用forever代替
A program can call a task or function in modules or other programs. But a module can not call a task or function in a program
Systemverilog把整个环境执行顺序分成Active->Observed->Reactive->Postponed,在同一个time slot里(同一时刻)然后按照这个顺序执行:DUT-》Assertions-》Testbench。
而我在http://www.project-veripage.com/program_blocks_3.php看到的是它多加了一个区域叫做Non-BLocking的区域,这个区域就是Program中non-blocking assignments(应该就是赋值给interface并传递给DUT的)
然后我仿真了《systemverilog for verification》中第四章的例子:
module memory(input logic start,write,
input logic [7:0] addr,data);
logic [7:0] mem[256];
always@(posedge start)
if(write)
mem[addr]<=data;
endmodule
module test(output logic start,write, //这里可以换成是program
output logic [7:0] addr,data);
initial begin
start = 0;
write = 0;
#10;
addr = 8'h42;
data = 8'h5a;
start = 1;
write = 1;
#2;
end
endmodule
module top();
logic start,write;
logic [7:0] addr,data;
memory memory(.*);
test test(.*);
endmodule
结果无论test我是用program还是module,memory中 ‘h42地址处都写进去了’h5A。 NC仿真器也是这样