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Xilinx spartan6 ODDR2的用法！

已有 38120 次阅读| 2012-3-17 21:35 |个人分类:FPGA

最近要用spartan6这个器件，听说比较高端。郁闷的是原来spartan3能放下的程序，spartan6不能放下，逻辑资源不够。重头一点一点的堆砌吧，在搞PLL的时候，又遇到PLL倍频输出的时钟不能直接连接到普通IO的问题。要命的是，板子上的dsp需要FPGA给出主时钟才能运行，硬件这样做好了，DSP要能工作，时钟必须要从那个引脚输出。刚开始，PLL的时钟直接连接到IO，map失败，一看原因，迫不及待在ucf文件中加入下面的约束：

PIN "U_CLOCK_PLL/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "U_CLOCK_PLL/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;

map的时候生成下面的警告。虽然得到了下载文件，尝试了几次，DSP连不上。无奈，只有按照ISE给出的建议：

WARNING:Place:1205 - This design contains a global buffer instance,<U_CLOCK_PLL/clkout2_buf>, driving the net, <dsp_clkin_OBUF>, that is driving the following (first 30) non-clock source pins off chip.
   < PIN: dsp_clkin.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution:

instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to.C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <U_CLOCK_PLL/clkout2_buf.O> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.

WARNING:Place:1205 - This design contains a global buffer instance, <U_CLOCK_PLL/clkout1_buf>, driving the net, <dsp_aeclkin_OBUF>, that is driving the following (first 30) non-clock source pins off chip.
   < PIN: dsp_aeclkin.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution:

   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to.C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <U_CLOCK_PLL/clkout1_buf.O> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.

WARNING:Place:1137 - This design is not guaranteed to be routable! This design contains a global buffer instance, <U_CLOCK_PLL/clkout2_buf>, driving the net, <dsp_clkin_OBUF>, that is driving the following (first 30) non-clock source pins. < PIN: dsp_clkin.O; > This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. Please pay extra attention to the timing and routing of this path to ensure the design goals are met. This is normally an ERROR but the
   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <U_CLOCK_PLL/clkout2_buf.O> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.

WARNING:Place:1137 - This design is not guaranteed to be routable! This design contains a global buffer instance, <U_CLOCK_PLL/clkout1_buf>, driving the net, <dsp_aeclkin_OBUF>, that is driving the following (first 30) non-clock source pins.< PIN: dsp_aeclkin.O; > This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. Please pay extra attention to the timing and routing of this path to ensure the design goals are met. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <U_CLOCK_PLL/clkout1_buf.O> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.

按照其中的说法：实例化一个ODDR2，这个小元件的详细介绍在xilinx参考文档ug381中有详细介绍。实例化的代码：

ODDR2 #(
    .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
    .INIT(1'b0),    // Sets initial state of the Q output to 1'b0 or 1'b1
    .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
    ) U_ODDR2_XXXHZ
(
      .Q(oddr2_xxxmhz),   // 1-bit DDR output data
      .C0(clock_xxxmhz),   // 1-bit clock input
      .C1(~clock_xxxmhz),   // 1-bit clock input
      .CE(1'b1), // 1-bit clock enable input
      .D0(1'b1), // 1-bit data input (associated with C0)
      .D1(1'b0), // 1-bit data input (associated with C1)
      .R(1'b0),   // 1-bit reset input
      .S(1'b0)    // 1-bit set input
);

信号oddr2_xxxmhz就是那个可以输出到普通IO的信号了。