WARNING:Place:1205 - This design contains a global buffer instance,<U_CLOCK_PLL/clkout2_buf>, driving the net, <dsp_clkin_OBUF>, that is driving the following (first 30) non-clock source pins off chip. < PIN: dsp_clkin.O; > This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to.C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <U_CLOCK_PLL/clkout2_buf.O> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
WARNING:Place:1205 - This design contains a global buffer instance, <U_CLOCK_PLL/clkout1_buf>, driving the net, <dsp_aeclkin_OBUF>, that is driving the following (first 30) non-clock source pins off chip. < PIN: dsp_aeclkin.O; > This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to.C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <U_CLOCK_PLL/clkout1_buf.O> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
WARNING:Place:1137 - This design is not guaranteed to be routable! This design contains a global buffer instance, <U_CLOCK_PLL/clkout2_buf>, driving the net, <dsp_clkin_OBUF>, that is driving the following (first 30) non-clock source pins. < PIN: dsp_clkin.O; > This is not a recommended design practice in Spartan-6 due to limitations in the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. Please pay extra attention to the timing and routing of this path to ensure the design goals are met. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <U_CLOCK_PLL/clkout2_buf.O> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
WARNING:Place:1137 - This design is not guaranteed to be routable! This design contains a global buffer instance, <U_CLOCK_PLL/clkout1_buf>, driving the net, <dsp_aeclkin_OBUF>, that is driving the following (first 30) non-clock source pins.< PIN: dsp_aeclkin.O; > This is not a recommended design practice in Spartan-6 due to limitations in the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. Please pay extra attention to the timing and routing of this path to ensure the design goals are met. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <U_CLOCK_PLL/clkout1_buf.O> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.