I am trying to do a mixed signal simulation with AMS under cadence\virtuoso.

this is for an old testbench which was working fine with Spectre simulator,
but then I replace a logic block with a verilog code instead of an old one with veriloga (then I need AMS).
the new Verilog block has no problem, as I am able to simulate it in a separate testbench.

when trying to run the testbench with AMS I got the error message

generate netlist...
### Generating design information at:/home/aalmaras/Spectre40/sdm_test_logic_run/.tempProjectDir/sdm_test_logic/ams/config/netlist ###
ERROR (45) : Cellview based netlisting has failed.
Check Simulation->Output Log->Netlister Log for errors.
Correct your design and netlist again.
...unsuccessful.

however in the Netlister Log I do not see any errors or even warnings

Netlisting ("tests" "sdm_test_logic" "config").

Info: Processing ("tsmcN40" "inv_lvt" "schematic") ...
Info: Found 0 errors and 0 warnings.

Info: Processing ("BlocksTr" "switiID" "schematic") ...
Info: Verilog-AMS netlist successfully written to
~/switiID/schematic/verilog.vams.
Info: Found 0 errors and 0 warnings.

Info: Processing ("BlocksTr" "mixed_lgc_tap2" "schematic") ...
Info: Verilog-AMS netlist successfully written to
~/mixed_lgc_tap2/schematic/verilog.vams.
Info: Found 0 errors and 0 warnings.

Info: Processing ("BlocksTr" "NO_clck" "schematicD_ID") ...
Info: Verilog-AMS netlist successfully written to
~/NO_clck/schematicD_ID/verilog.vams.
Info: Found 0 errors and 0 warnings.

Info: Processing ("SD_DAC" "SDM_DAC_lgcTap2" "schematic") ...
Info: Verilog-AMS netlist successfully written to
~/SDM_DAC_lgcTap2/schematic/verilog.vams.
Info: Found 0 errors and 0 warnings.

Info: Processing ("tests" "sdm_test_logic" "schematic") ...
Info: Verilog-AMS netlist successfully written to
~/sdm_test_logic/schematic/verilog.vams.
Info: Found 0 errors and 0 warnings.
Done netlisting ("tests" "sdm_test_logic" "config").

and no netlist is generated ....
do you have any suggestions/ comments

Solution：
As I found the solution I post it here, in case sb needed it
so it seems that the AMS simulator wants to get a write access for all schematics in the design hierarchy.
and since I was using some predefined ones from my Tech. Library this was preventing the netlist.
so, when copied into new cell-views, the issue was resolved

from：