日志
[ZZ]SPICE and FastSPICE Vendors
| |
Before SPICE
In 1967 a circuit simulation program called BIAS was developed by Howard [1], followed by CANCER from Nagel while in a research group of Rohrer.
SPICE
Professor Pederson's class created SPICE (Simulation Program with Integrated Circuit Emphasis) in 1971 to simulate the timing and power of ICs, then released SPICE publicly in 1972. The original versions of SPICE are available from Berkeley under a BSD licence that allows for modification and sale (without having to share the source), so many companies have used at as the base of a simulator. Newer simulators and "fast" SPICE simulators may use different internals but read the same netlists (for which there is no official standard).
Circuit designers typically use a schematic capture tool to enter their design at the transistor-level, create a netlist, then simulate the design in SPICE and visualize the voltage and current waveforms with a viewer.
In 1967 a circuit simulation program called BIAS was developed by Howard [1], followed by CANCER from Nagel while in a research group of Rohrer.
SPICE
Professor Pederson's class created SPICE (Simulation Program with Integrated Circuit Emphasis) in 1971 to simulate the timing and power of ICs, then released SPICE publicly in 1972. The original versions of SPICE are available from Berkeley under a BSD licence that allows for modification and sale (without having to share the source), so many companies have used at as the base of a simulator. Newer simulators and "fast" SPICE simulators may use different internals but read the same netlists (for which there is no official standard).
Introduction
Circuit designers typically use a schematic capture tool to enter their design at the transistor-level, create a netlist, then simulate the design in SPICE and visualize the voltage and current waveforms with a viewer.
[hide] - [top]Analysis
Engineers run multiple analysis simulations to answer questions about
the performance of their design versus the specification that they are
trying to meet or exceed:
- DC (Direct Current)
- AC (Alternating Current)
- Transient
- Monte Carlo
- Sensitivity
- Noise
- Reliability
- Harmonic balance
- Periodic steady state
- Optimization
- ERC (Electrical Rule Check)
[hide] - [top]EDA Vendors
Here's a list of EDA vendors offering SPICE, and FastSPICE circuit
simulators. Let me know if I missed any and I'll update the post.
[hide] - [top]SPICE
|-|-|-
| Tool | Company | Inputs | Analysis | Comments |
| ADS Transient Convolution | Agilent EEsof EDA | Schematic, ADS, SPICE, Spectre, HSPICE, verilog-A | DC, Transient, AC, noise (Harmonic balance and circuit envelope options) | Device models (BSIM, etc.). DES encryption. Integration with frequency domain (via causal convolution) and distributed transmission line elements (multi layer models library, Momentum multilayer 3DEM, FEM abitrary geometry 3DEM). Schematic capture. Data display. Traditional IBIS. Time-domain (bit-by-bit) and statistical channel simulators with eye diagram and IBIS AMI flow. Jitter decomposition. Broadband SPICE model generator. Measurement hardened. |
| HSPICE | Synopsys | HSPICE, Verilog-A | DC, Transient, AC, Frequency, MC, MOSRA, ACMatch, DCMatch, RF (HSPICE RF), loop stability, transient noise | Device models (BSIM, PSP, HiSIM, HVMOS, TFT, etc.). Triple DES encryption. Integration with Synopsys Custom Designer, Custom Waveview. Integration with Cadence virtuoso Analog Design Environment (ADE). W-element. Statistical eye diagram (with IBIS AMI). |
| Virtuoso Spectre | Cadence | Spectre, SPICE, Verilog-A 2.0, S-parameter data files | DC, Transient, AC, Frequency, MC, noise, transfer function, sensitviity, transient noise, reliability, harmonic balance, periodic and quasi-periodic steady state, periodic and quasi-periodic small signal, time domain and frequency domain envelope, RF with turbo | analog, RF, mixed-signal, integrated with Virtuoso custom design platform, co-simulation with Simulink. Webinar blog, November 2011. |
| PSpice | Cadence | OrCAD, Allegro Design Entry-hdl | DC, Transient, AC, MC, Smoke, temperature, stress, sensitivity, optimizer | Power supplies, high-frequency, simple IC designs, integrated with OrCAD Capture, MATLAB Simulink for co-simulation, PCB flow integration |
| Virtuoso APS | Cadence | Spectre, SPICE, Verilog-A, S-parameter data files | DC, Transient, AC, transient noise, relibility, MC, RF harmonic balance, RF shooting Newton, RF FAST envelope, RF noise and small signal | scalable multi-core simulation, analog and RF designs. Webinar blog, November 2011. |
| Eldo Classic | Mentor | Eldo, HSPICE, Verilog-A, Spectre | DC, Transient, AC, Noise, transfer function, loop stability, incremental Monte Carlo, Safe Opeating Area analysis, Hi-Z checks, transient noise, DC mismatch, aging, AC, DC sensitivity, AC sensitivity, transient sensitivity, aging sensitivity, pole-zero analysis, large signal multi-tone steady-state analysis, phase noise, non-linear contribution analysis, modulated steady-state analysis | Scalable multi-threading, integrated with Mentor and Cadence frameworks, up to 1M devices, RLCCK parasitic reduction, dspF backannotation, distributed to multi-cpus (LSF, Grid and proprietary dispatchers), built-in optimization, bisection, waveform. outputs (.wdb, .tr0, .psf, .fsdb), analog and digital macro models, all standard models (BSIM3, BSIM4, PSP, HiSIM, HiSIM/HV, EKV, HICUM, VBIC, MEXTRAM, BSIMSOI, TFT), IBIS 5.0, S-parameters, microstrip models, lossy and lossless transmission lines, API for proprietary model integration, optional netlist case-sensitivity, integrated with Questa-AMS for mixed-signal verification |
| FineSim SPICE | Synopsys | HSPICE, Spectre, Eldo | DC, transient, AC, MC | Multi-cpu. Outputs (FineWave, tr0, fsdb, wdf). Integrated with SiliconSmart library characterization products. Acquired from Magma. |
| RASER | Infinisim | |||
| SmartSpice | Silvaco | |||
| T-Spice | Tanner EDA | HSPICE, PSpice | DC, transient, AC, MC | Multi-threaded. Model support: PSP, BSIM3.3, BSIM4.6, BSIM SOI 4.0, EKV 2.6, MOS 9, RPI a-Si & Poly-Si TFT, BMIC, MEXTRAM. |
| MSIM | Legend Design | SPICE, Verilog-A | DC, transient, AC, MC | Multi-threaded, multi-core. TSMC certified. Built-in RC reduction. Model support (BSIM3, BSIM4, HiSim, TFT, BJT, diode, RPI, s-parameter, IBIS, etc.). Outputs: wdf, fsdb, tr0, ascii. |
| ACCIT | ACCIT New Systems Research | GPU powered. | ||
| Ngspice | Open Source | |||
| Qucs | Open Source | GUI and schematics | ||
| SIMetrix SPICE | SIMetrix | (also SIMPLIS for PLL, switching, complex modulation simulation) | ||
| XSpice | Altium | bundled inside of Altium Designer, PCB focus. | ||
| IsSpice4 | Intusoft | |||
| CoolSpice | CoolCAD Electronics | DC, transient, AC. Model support (in free student version): MOS1 (level 1), MOS2 (level 2), MOS3 (level 3), BSIM1 (level 4), BSIM2 (level 5), MOS6 (level 6), MOS7 (level 7), BSIM3 (level 8/49) (3.0=3.0, 3.1=3.1, 3.2=3.2.4, 3.3=3.3.0), MOS9 (level 9), BSIM4 (level 4/54) (4.0=4.2.1, 4.1=4.2.1, 4.2=4.2.1, 4.3=4.3.0, 4.4=4.4.0, 4.5=4.5.0, 4.6=4.6.2), B3SOIFD (level 55), B3SOIDD (level 56), B3SOIPD (level 57), B4SOI (level 10/58), SOI3 (level 60). Cryogenic CMOS models and high-temp.-high-power silicon carbide (SiC) device models in the commercial version. Commercial version supports 3D-thermal-electrical simulations for SiC devices. | ||
| LTspice IV | Linear Technology | Focus on switching regulators, includes schematics and waveform. viewer. | ||
| NI Multisim | National Instruments | Part of Electronics Workbench. | ||
| TINA Pro | DesignWare Inc | PCB layout, schematics, simulation. | ||
| Nexxim | Ansys | simulator inside of Designer, SI and RF simulation focus. | ||
| SymSpice | SYMICA | HSPICE, Spectre, Verilog-A | DC, AC, Transient, Sweep, MC | Start-up from San Jose (V1.02, April 2011). HiSIM HV models. Schematic capture (Q1 2012). |
| NanoDesigner | Proplus | Spin-out from Cadence/Celestry in 2007 | ||
| Micro-Cap | Spectrum Software | Integrated schematic editor and SPICE simulator, founded in 1980 | ||
| 5Spice | 5Spice | PSpice | DC, AC, Transient | Discrete level simulation with schematics and waveform. viewing. Free download with restricted features. |
[hide] - [top]Historic SPICE Simulators
| Tool | Company | Inputs | Analysis | Comments |
| Syscap | ||||
| ECAP | IBM | Used in the 1960s. | ||
| BELAC |
[hide] - [top]Analog FastSPICE
|-
| Tool | Company | Inputs | Analysis | Comments |
| Analog FastSPICE Platform | Berkeley Design Automation | SPICE (HSPICE and Spectre netlist and simulator options); DSPF; Verilog-A | DC,
transient, AC, pole/zero, S-parameter analysis, .NET multiport,
stability analysis, small signal transfer function (tf/xf), noise
analysis. AFS Co-sim option (HDL co-simulation with Verilog). AFS Transient Noise option (transient noise analysis). AFS RF option (pss, pnoise, pstb, pac, pxf, oscpss/oscnoise, vcopss/vconoise analyses); Harmonic Balance (hbpss, hbnoise, hbpac, hbpxf analyses). | >10M element
capacity; accuracy from nanometer SPICE to near SPICE; multithreaded for
single simulation runs and MultiCore Parallel (MCP) for repeated runs
(Monte Carlo, sweeps, alter, etc); WaveCrave and CalcPad viewing and
post-processing. AFS Nano (same core simulator, capacity 5k elements). Fully integrated into Cadence's ADE. Model support includes BSIM3, BSIM4, BSIMSOI, PSP, MOS1/3, MOS9, MOS11, Mextram, HICUM, HiSIM_HV, VBIC, JFET, diode, juncap, BJT, Gummel-Poon, physical resistor, fracpole, tline, S-parameter, W-element. Netlist and model encryption. |
| PCSIM | Cybereda | SPICE | DC, transient | Parallel, multi-cpu, million device capacity, model support (BSIM3, BSIM4, BJT, diode), viewer support (nWave - SpringSoft, anaWave - AnaGlobe, Berkeley Nutmeg) |
| Eldo Premier | Mentor | Eldo, HSPICE, Spectre, Verilog-A | DC, Transient, incremental Monte Carlo, Aging, Safe Operating Area | 10M
devices capacity, 2.5x to 20x faster than Eldo Classic with identical
accuracy, native multi-threading, integrated with Mentor and Cadence
frameworks, RLCCK parasitic reduction, DSPF backannotation, distributed
to multi-cpus (LSF, Grid and proprietary dispatchers), built-in
optimization, bisection, waveform. outputs (.wdb, .tr0, .psf, .fsdb),
analog and digital macro models, all standard models (BSIM3, BSIM4, PSP,
HiSIM, HiSIM/HV, EKV, HICUM, VBIC, MEXTRAM, BSIMSOI, TFT),
S-parameters, microstrip models, lossy and lossless transmission lines,
API for proprietary model integration, optional netlist
case-sensitivity, integrated with Questa-AMS for mixed-signal
verification |
[hide] - [top]Analog but not based on Berkeley SPICE
| Tool | Company | Inputs | Analysis | Comments |
| Gnucap | Open Source | SPICE compatible |
[hide] - [top]FastSPICE
|-
| Tool | Company | Inputs | Analysis | Comments |
| HSIM | Synopsys | HSPICE, Verilog-A, Spectre, Eldo, VCD, parasitics (DPF, SPEF, DSPF) | AC, DC, transient, MC, FFT | Hierarchical, built-in RCC reduction, integrated with Cadence Virtuoso, XA option (new engine) |
| NanoSIM | Synopsys | SPICE, HSPICE, Verilog, EDIF, LSIM, parasitics (SPF, SPEF) | AC, DC, transient, interactive, function checks, power analysis, timing analysis | model support (BJT, BSIM3, BSIM4, MM905, JFET, MESFET, HVMOS, SiGe VBIC, SOI), Cadence integration, TurboWave integration, co-simulation with Verilog (VCS), XA option (new engine) |
| CustomSim | Synopsys | HSPICE, Spectre, Eldo, Verilog-A, parasitics (SPF, DPF, SPEF), VCD | AC, DC, transient, MC, interactive, function checks, power analysis, timing analysis | Combined: HSIM, NanoSim, XA. Tcl scripting. Outputs (WDF, WDB, FSDB, etc.). Models (HSPICE, Spectre, Eldo). |
| Virtuoso UltraSim | Cadence | SPICE, Spectre, Veilog-A, DSPF, SPEF, Verilog-AMS, VHDL-AMS, Verilog, VHDL, PLI, SystemC, SystemVerilog | ERC, Power, Timing, Node Activity | Hierarchical, integrated with Virtuoso Layout |
| ADiT | Mentor | Eldo, HSPICE, Spectre, Verilog-A, parasitics (DSPF, SPF), VCD | DC, transient, MC, reliability (aging), Hi-Z and leakage | 10 million device capacity, Outputs (.wdb, .fsdb, ADit, .tr0, .tb0), integrated with Cadence Virtuoso, waveform. (EZwave), RC reduction, mixed-signal simulation with Questa ADMS, save/restart |
| FineSim PRO | Magma | HSPICE, Spectre, Eldo, parasitics (DSPF) | DC, transient, AC, MC, EM (option) | Multi-CPU. Models (electrically exact, BSIM3, BSIM4, BSIM-SOI, Phillips MM9, Gummel-Poon, VBIC 1.2, Philips Mextram 503, Diode, RLC, inverted inductance). Outputs (.tr0, fsdb, wdf). Co-simulation (Verilog, VHDL). RC reduction. SiliconSmart library characterization integration. |
| Turbo MSIM | Legend Design | SPICE, HSPICE | DC, transient, AC, MC | Hierarchical. Built-in RC reduction. Device models (BSIM3, BSIM4, BJT, diode). Outputs (wdf, fsdb, ascii). |
[hide] - [top]References
1. From nano to space: applied mathematics inspired by Roland Bulirsch By Roland Bulirsch, Michael H. Breitner, Georg Denk, Peter Rentrop
/1 
eetop公众号
创芯大讲堂
创芯人才网