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[原创]IC design flow & relevant desing tools!
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仅供参考，欢迎大家补充和指正。
| Design Flow | Design Details | Tools | Company |
| Code Editors/Doc Editors | Vi/Vim | GNU | |
| Emacs | GNU | ||
| FrameMake | Adobe | ||
| Office | Microsoft | ||
| FrontEnd | Simulation | VCS | Sunopsys |
| NC-Verilog(IUS) | Cadence | ||
| Verilog XL | Cadence | ||
| ModelSim | Mentor | ||
| Debug | Debussy | SpringSoft/Novas | |
| Verdi | SpringSoft/Novas | ||
| Simvision | Cadence | ||
| DVE | Synopsys | ||
| Lint Checking | HAL | Cadence | |
| SpyGlass | Atrenta | ||
| 0-in Checklist | Archer | ||
| nLint | SpringSoft/Novas | ||
| Equivalence Checking | LEC | Cadence/Verplex | |
| Conformal ASIC | Cadence | ||
| SLV | Cadence | ||
| Coverage | HDLScore | Summit | |
| ICC | Cadence | ||
| InfiniteStream | Cacence | ||
| VCS Coverage Metrics | Synopsys | ||
| Formal Verification | Fromality | Synopsys | |
| BlackTie | Cadence/Verplex | ||
| IFV | Cadence | ||
| SV Verification | Open Vera | Synopsys | |
| Specman Elite | Verisity | ||
| VCS/SystemVerilog | Synopsys | ||
| Incisive | Cadence | ||
| Questa | Mentor | ||
| Assertion Based Verification | SVA | ||
| OVL | |||
| CBV | |||
| CDC | 0-In CDC | Mentor | |
| ECO | nECO | SpringSoft/Novas | |
| Low Power Analysis | Power Compiler | Synopsys | |
| Power Theater | Sequence | ||
| Emulation | Palladium | Cadence | |
| FrontEnd-BackEnd | Synthesis | Design Compiler | Synopsys |
| RTL Compiler | Cadence | ||
| Physical Compiler | Synopsys | ||
| STA | PrimeTime | Synopsys | |
| DFT | DFT Compiler | Synopsys | |
| BSD Compiler | Synopsys | ||
| DFT MAX | Synopsys | ||
| TetraMAX ATPG | Synopsys | ||
| BackEnd | P&R | Encounter | Cadence |
| Silicon Ensemble | Cadence | ||
| IC Compiler | Synopsys | ||
| Appollo | |||
| Magma | Magma | ||
| LVS/DRC | Dracula | Cadence | |
| Hercules | Synopsys | ||
| Calibre | Mentor Graphics | ||
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