日志
verilog system task $stop and $finish
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天气: 热
心情: 平静
$stop: put the simulation into a halt mode, pass control to user.$finish: causes the simulator to exit and pass control back to the host OS.
parameter:
0: prints nothing
1:prints simulation time and location
2:pint simulation time and location, statistics about the memory and cpu time used in the simulation.
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