---1.1 Transaction-Level Modeling
1.A model of time
2.Abstraction Methods of communication between concurrent processes
3.Rules for process activation

Abstract time
  The time abstraction in a simulator refers to how often the entire design state is consistent
Abstract data
  Data refers to the objects communicated between components.
Abstract function
  The function of a model is the set of all things it must do at each event.

---1.2 Definition of a Transaction
A transaction is a quantum of activity that occurs in a design bounded by time.
(This is the most general definition of a transaction)

A transaction is a single transfer of control or data between two entities.
(This is the hardware-oriented notion of a transaction)

A transaction is a function call.
(This definition is the software-oriented notion of a transaction.)

---1.3 Interfaces
 The term interface is used in several ways in OVM, each with a slightly different meaning. It’s an unfortunate fact of history that the same word has come to mean so many different things.

SystemVerilog interface
  SystemVerilog provides a construct called an interface, which is one of the primary container objects from which you construct a design in SystemVerilog.

Object interface
 There are two slight variations of this meaning of interface.
 (1)  Look at a class and determine what tasks and functions are available to the user of the class to operate it.That’s its interface.
 (2)  The other variation is to refer to a base class that defines the set of tasks and functions available to operate the derived class.

DUT interface
 A piece of hardware is typically accessed through its interfaces. In this context, an interface is composed of the pins and protocol used to communicate to the device.

---1.4  TLM Idioms
put