日志
- 分享 CONV CONV
- //CONV build in a 3*3 convolution core //for 6*6 input data module CONV( input wire reset, input wire clk, input wire CONV_start, output reg CONV_finish, input wire signed CONV_iData, output reg signed CONV_oData ); reg signed CONV_core ; ...
- 分享 卷积计算
- 卷积计算 目录 1. 问题分析 2. 工作框图 3. 工作方式 4. 数据选取 5. 文件说明 6. 端口说明 7. 工作说明 8. 仿真说明 9. 仿真结果 1) 波形 2) Transcript 10. Matlab 验证 1. 问题分析 构造一个 3*3 的卷积核，并利用该 ...
- 分享 AHBAPB wave.do
- onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate /TOP_TB/DUT_TOP/HADDR0 add wave -noupdate /TOP_TB/DUT_TOP/HADDR1 add wave -noupdate /TOP_TB/DUT_TOP/HADDR2 add wave -noupdate /TOP_TB/DUT_TOP/HADDR3 add wave -noupdate /TOP_TB/DUT_TOP/HBYTEN0 add wave -noupdate /TOP_TB/DUT ...
- 分享 AHBAPB TOP_TB
- // TOP module // define BRIDGE ARBITOR DECODER SLAVE `timescale 1us/1us module TOP_TB( ); reg RESETn; reg CLK; // TEST reg TStart; reg TENx; reg TWRITEn; reg HBYTEN0; reg HBYTEN1; reg HBYTEN2; reg& ...
- 分享 AHBAPB TOP
- // TOP module // define BRIDGE ARBITOR DECODER SLAVE module TOP( input wire RESETn, input wire CLK, // TEST input wire TStart, input wire TENx, input wire TWRITEn, input wire HBYTEN0, input wire HBYTEN1, input wire HBYTEN2, ...
- 分享 AHBAPB Decoder
- module Decoder #(parameter width = 32)( input wire DAT0, input wire DAT1, input wire DAT2, input wire DAT3, output reg DATo, input wire MASTER ); always @(*) begin case(MASTER) 4'h0: DATo = DAT0; 4'h1:&nbs ...
- 分享 AHBAPB APB_Slave
- module APB_Slave( input wire PRESETn, input wire PCLK, input wire PSELx, input wire PENABLE, input wire PWRITE, input wire PADDR, input wire PWDATA, output reg PRDATA ); reg Slave_Data ; /* S0: 0x0000_0000 ~ 0x0000_00ff; S1: 0x0000_0100 ~ 0x0000_0 ...
- 分享 AHBAPB APB_Bridge
- `define IDLE 2'b00 `define SETUP 2'b01 `define ENABLE 2'b10 module APB_Bridge( input wire PRESETn, input wire PCLK, // AHB input wire HEN, input wire HRWN, input wire HBYTEN, input wire HADDR, input wire HWDATA, output reg HRDATA, output reg HREADY ...
- 分享 AHBAPB AHB_Master
- module AHB_Master( input wire HRESETn, input wire HCLK, input wire TStart, input wire TEN, input wire TWRITEn, output reg HBUSREQ, input wire HGRANT, input wire HKGrant, output reg HEN, output reg HRWN, input wire HREADY, input wire HACK ); reg AHB_Load; always @(po ...
- 分享 AHBAPB AHB_Arbiter
- module AHB_Arbiter( input wire HRESETn, input wire HCLK, input wire HBUSREQx, output reg HGRANTx, input wire HADDR, input wire HREADY, input wire HKGrant, output reg HMASTER ); reg State_A; reg REQi; reg GRANTo; reg GRANT_nx; // roll the Input Re ...
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