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AHBAPB TOP_TB

已有 408 次阅读| 2019-2-28 19:23 |系统分类:芯片设计

// TOP module

// define BRIDGE ARBITOR DECODER SLAVE

`timescale 1us/1us

module TOP_TB( );

reg RESETn;

reg CLK;

// TEST

reg TStart;

reg [3:0] TENx;

reg TWRITEn;

reg [1:0] HBYTEN0;

reg [1:0] HBYTEN1;

reg [1:0] HBYTEN2;

reg [1:0] HBYTEN3;

reg [31:0] HADDR0;

reg [31:0] HADDR1;

reg [31:0] HADDR2;

reg [31:0] HADDR3;

reg [31:0] HWDATA0;

reg [31:0] HWDATA1;

reg [31:0] HWDATA2;

reg [31:0] HWDATA3;

TOP DUT_TOP(

.RESETn (RESETn),

.CLK (CLK),

.TStart (TStart),

.TENx (TENx),

.TWRITEn (TWRITEn),

.HBYTEN0 (HBYTEN0[1:0]),

.HBYTEN1 (HBYTEN1[1:0]),

.HBYTEN2 (HBYTEN2[1:0]),

.HBYTEN3 (HBYTEN3[1:0]),

.HADDR0 (HADDR0[31:0]),

.HADDR1 (HADDR1[31:0]),

.HADDR2 (HADDR2[31:0]),

.HADDR3 (HADDR3[31:0]),

.HWDATA0 (HWDATA0[31:0]),

.HWDATA1 (HWDATA1[31:0]),

.HWDATA2 (HWDATA2[31:0]),

.HWDATA3 (HWDATA3[31:0])

);

/*******************/

/* Main Simulation */

/*******************/

initial

begin

$display("Test Init");

TStart = 1'b0;

TENx = 4'b0;

TWRITEn = 1'b1;

HBYTEN0 = 2'h2;

HBYTEN1 = 2'h2;

HBYTEN2 = 2'h2;

HBYTEN3 = 2'h2;

HADDR0 = 32'h00000000;

HADDR1 = 32'h00000000;

HADDR2 = 32'h00000000;

HADDR3 = 32'h00000000;

HWDATA0 = 32'h00000000;

HWDATA1 = 32'h00000000;

HWDATA2 = 32'h00000000;

HWDATA3 = 32'h00000000;

RESETn = 0;

CLK = 0;

#9 RESETn = 1;

$display("Test Start");

$display("\n1 TEST Normal (Write) : Master 0 Write 0 (Arbiter now primary-0) ");

#1 TStart = 1'b1; TENx = 4'b0001; TWRITEn = 1'b0;

HADDR0 = 32'h0000_00_08; HWDATA0 = 32'h55555555;

#3 TStart = 1'b0;

#40

$display("\n2 TEST Normal (Read ) : Master 1 Read 0 (Arbiter now primary-1) ");

#1 TStart = 1'b1; TENx = 4'b0010; TWRITEn = 1'b1;

HADDR1 = 32'h0000_00_08;

#3 TStart = 1'b0;

#40

$display("\n3 TEST All (Write) : Master 2->3->0->1 Write 2301 (Arbiter now primary-2) ");

#1 TStart = 1'b1; TENx = 4'b1111; TWRITEn = 1'b0;

HADDR0 = 32'h0000_00_10; HWDATA0 = 32'h0A0A0A0A;

HADDR1 = 32'h0000_01_10; HWDATA1 = 32'h1B1B1B1B;

HADDR2 = 32'h0000_02_10; HWDATA2 = 32'h2C2C2C2C;

HADDR3 = 32'h0000_03_10; HWDATA3 = 32'h3D3D3D3D;

#3 TStart = 1'b0;

#160

$display("\n4 TEST All (Read ) : Master 2->3->0->1 Read 1032 (Arbiter now primary-2) ");

#1 TStart = 1'b1; TENx = 4'b1111; TWRITEn = 1'b1;

HADDR0 = 32'h0000_03_10;

HADDR1 = 32'h0000_02_10;

HADDR2 = 32'h0000_01_10;

HADDR3 = 32'h0000_00_10;

#3 TStart = 1'b0;

#160

$display("\n5 TEST Normal (Write) : Master 3 Write 1 (Arbiter now primary-1) ");

#1 TStart = 1'b1; TENx = 4'b1000; TWRITEn = 1'b0;

HADDR3 = 32'h0000_01_20; HWDATA3 = 32'h11111111;

#3 TStart = 1'b0;

#40

$display("\n6 TEST Normal (Write) : Master 2 Write 2 (Arbiter now primary-2) ");

#1 TStart = 1'b1; TENx = 4'b0100; TWRITEn = 1'b0;

HADDR2 = 32'h0000_02_20; HWDATA2 = 32'h22222222;

#3 TStart = 1'b0;

#40

$display("\n7 TEST Normal (Write) : Master 1 Write 3 (Arbiter now primary-3)");

#1 TStart = 1'b1; TENx = 4'b0010; TWRITEn = 1'b0;

HADDR1 = 32'h0000_03_20; HWDATA1 = 32'h33333333;

#3 TStart = 1'b0;

#40

$display("\n8 TEST Normal (Read ) : Master 2 Read 1 (Arbiter now primary-1) ");

#1 TStart = 1'b1; TENx = 4'b0100; TWRITEn = 1'b1;

HADDR2 = 32'h0000_01_20;

#3 TStart = 1'b0;

#40

$display("\n9 TEST Normal (Read ) : Master 1 Read 2 (Arbiter now primary-2) ");

#1 TStart = 1'b1; TENx = 4'b0010; TWRITEn = 1'b1;

HADDR1 = 32'h0000_02_20;

#3 TStart = 1'b0;

#40

$display("\n10TEST Normal (Read ) : Master 3 Read 3 (Arbiter now primary-3) ");

#1 TStart = 1'b1; TENx = 4'b1000; TWRITEn = 1'b1;

HADDR3 = 32'h0000_03_20;

#3 TStart = 1'b0;

#40

$display("\nTest Stop");

#100 $stop;

end

// CLK for master, slave

always #2 CLK = !CLK;

endmodule

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