日志
AHBAPB TOP
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// TOP module
// define BRIDGE ARBITOR DECODER SLAVE
module TOP(
input wire RESETn,
input wire CLK,
// TEST
input wire TStart,
input wire [3:0] TENx,
input wire TWRITEn,
input wire [1:0] HBYTEN0,
input wire [1:0] HBYTEN1,
input wire [1:0] HBYTEN2,
input wire [1:0] HBYTEN3,
input wire [31:0] HADDR0,
input wire [31:0] HADDR1,
input wire [31:0] HADDR2,
input wire [31:0] HADDR3,
input wire [31:0] HWDATA0,
input wire [31:0] HWDATA1,
input wire [31:0] HWDATA2,
input wire [31:0] HWDATA3
);
// master
wire [3:0] HBUSREQx;
wire [3:0] HENx;
wire [3:0] HRWNx;
wire [3:0] HGRANTx;
wire [1:0] HBYTEN;
wire [31:0] HADDR;
wire [31:0] HWDATA;
wire [31:0] HRDATA;
wire HREADY;
wire HACK;
wire HKGrant;
wire HdERROR;
wire [3:0] HMASTER;
assign HEN = HENx[0] | HENx[1] | HENx[2] | HENx[3];
assign HRWN = HRWNx[0] & HRWNx[1] & HRWNx[2] & HRWNx[3];
// slave
wire PSEL0,PSEL1,PSEL2,PSEL3;
wire PENABLE;
wire PWRITE;
wire [31:0] PADDR;
wire [31:0] PWDATA;
wire [31:0] PRDATA, PRDATA0, PRDATA1, PRDATA2, PRDATA3;
wire [3:0] PMASTER;
/////////////////////////
/* define relationship */
/////////////////////////
AHB_Master TEST_Master0(
.HRESETn (RESETn),
.HCLK (CLK),
.TStart (TStart),
.TEN (TENx[0]), //
.TWRITEn (TWRITEn),
.HBUSREQ (HBUSREQx[0]), //
.HGRANT (HGRANTx[0]), //
.HKGrant (HKGrant),
.HEN (HENx[0]), //
.HRWN (HRWNx[0]), //
.HREADY (HREADY),
.HACK (HACK)
);
AHB_Master TEST_Master1(
.HRESETn (RESETn),
.HCLK (CLK),
.TStart (TStart),
.TEN (TENx[1]), //
.TWRITEn (TWRITEn),
.HBUSREQ (HBUSREQx[1]), //
.HGRANT (HGRANTx[1]), //
.HKGrant (HKGrant),
.HEN (HENx[1]), //
.HRWN (HRWNx[1]), //
.HREADY (HREADY),
.HACK (HACK)
);
AHB_Master TEST_Master2(
.HRESETn (RESETn),
.HCLK (CLK),
.TStart (TStart),
.TEN (TENx[2]), //
.TWRITEn (TWRITEn),
.HBUSREQ (HBUSREQx[2]), //
.HGRANT (HGRANTx[2]), //
.HKGrant (HKGrant),
.HEN (HENx[2]), //
.HRWN (HRWNx[2]), //
.HREADY (HREADY),
.HACK (HACK)
);
AHB_Master TEST_Master3(
.HRESETn (RESETn),
.HCLK (CLK),
.TStart (TStart),
.TEN (TENx[3]), //
.TWRITEn (TWRITEn),
.HBUSREQ (HBUSREQx[3]), //
.HGRANT (HGRANTx[3]), //
.HKGrant (HKGrant),
.HEN (HENx[3]), //
.HRWN (HRWNx[3]), //
.HREADY (HREADY),
.HACK (HACK)
);
AHB_Arbiter DUT_Arbiter(
.HRESETn (RESETn),
.HCLK (CLK),
.HBUSREQx (HBUSREQx[3:0]),
.HGRANTx (HGRANTx[3:0]),
.HADDR (HADDR[31:0]),
.HREADY (HREADY),
.HKGrant (HKGrant),
.HMASTER (HMASTER[3:0])
);
Decoder #(.width(2)) DUT_Decoder_BYTEN(
.DAT0 (HBYTEN0[1:0]),
.DAT1 (HBYTEN1[1:0]),
.DAT2 (HBYTEN2[1:0]),
.DAT3 (HBYTEN3[1:0]),
.DATo (HBYTEN[1:0]),
.MASTER (HMASTER[3:0])
);
Decoder DUT_Decoder_HADDR(
.DAT0 (HADDR0[31:0]),
.DAT1 (HADDR1[31:0]),
.DAT2 (HADDR2[31:0]),
.DAT3 (HADDR3[31:0]),
.DATo (HADDR[31:0]),
.MASTER (HMASTER[3:0])
);
Decoder DUT_Decoder_HWDATA(
.DAT0 (HWDATA0[31:0]),
.DAT1 (HWDATA1[31:0]),
.DAT2 (HWDATA2[31:0]),
.DAT3 (HWDATA3[31:0]),
.DATo (HWDATA[31:0]),
.MASTER (HMASTER[3:0])
);
APB_Bridge DUT_Bridge(
.PRESETn (RESETn),
.PCLK (CLK),
// AHB
.HEN (HEN),
.HRWN (HRWN),
.HBYTEN (HBYTEN[1:0]),
.HADDR (HADDR[31:0]),
.HWDATA (HWDATA[31:0]),
.HRDATA (HRDATA[31:0]),
.HREADY (HREADY),
.HACK (HACK),
.HKGrant (HKGrant),
.HdERROR (HdERROR),
// APB_Slave
.PSEL0 (PSEL0),
.PSEL1 (PSEL1),
.PSEL2 (PSEL2),
.PSEL3 (PSEL3),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PADDR (PADDR[31:0]),
.PWDATA (PWDATA[31:0]),
.PRDATA (PRDATA[31:0]),
.PMASTER (PMASTER[3:0])
);
Decoder DUT_Decoder_PRDAT(
.DAT0 (PRDATA0[31:0]),
.DAT1 (PRDATA1[31:0]),
.DAT2 (PRDATA2[31:0]),
.DAT3 (PRDATA3[31:0]),
.DATo (PRDATA[31:0]),
.MASTER (PMASTER[3:0])
);
APB_Slave DUT_APB_0(
.PRESETn (RESETn),
.PCLK (CLK),
.PSELx (PSEL0),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PADDR (PADDR[31:0]),
.PWDATA (PWDATA[31:0]),
.PRDATA (PRDATA0[31:0])
);
APB_Slave DUT_APB_1(
.PRESETn (RESETn),
.PCLK (CLK),
.PSELx (PSEL1),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PADDR (PADDR[31:0]),
.PWDATA (PWDATA[31:0]),
.PRDATA (PRDATA1[31:0])
);
APB_Slave DUT_APB_2(
.PRESETn (RESETn),
.PCLK (CLK),
.PSELx (PSEL2),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PADDR (PADDR[31:0]),
.PWDATA (PWDATA[31:0]),
.PRDATA (PRDATA2[31:0])
);
APB_Slave DUT_APB_3(
.PRESETn (RESETn),
.PCLK (CLK),
.PSELx (PSEL3),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PADDR (PADDR[31:0]),
.PWDATA (PWDATA[31:0]),
.PRDATA (PRDATA3[31:0])
);
endmodule
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