module Decoder
#(parameter width = 32)(
input wire [width-1:0] DAT0,
input wire [width-1:0] DAT1,
input wire [width-1:0] DAT2,
input wire [width-1:0] DAT3,
output reg [width-1:0] DATo,
input wire [3:0] MASTER
);
always @(*)
begin
case(MASTER)
4'h0: DATo = DAT0;
4'h1: DATo = DAT1;
4'h2: DATo = DAT2;
4'h3: DATo = DAT3;
default: DATo = 0;
endcase
end
endmodule