日志
AHBAPB AHB_Master
| |
module AHB_Master(
input wire HRESETn,
input wire HCLK,
input wire TStart,
input wire TEN,
input wire TWRITEn,
output reg HBUSREQ,
input wire HGRANT,
input wire HKGrant,
output reg HEN,
output reg HRWN,
input wire HREADY,
input wire HACK
);
reg AHB_Load;
always @(posedge HCLK or negedge HRESETn)
begin
if(!HRESETn)
begin
HBUSREQ <= 1'b0;
HEN <= 1'b0;
HRWN <= 1'b1;
//BYTEN <= 2'h3;
//ADDR <= 32'h00000000;
//WDATA <= 32'h00000000;
AHB_Load<= 1'b0;
end
else
begin
if(TStart & TEN)
begin
HBUSREQ <= 1'b1;
$display("%m Grant Waiting...");
end
if(HGRANT)
begin
if(HACK)
begin
AHB_Load<= 1'b0;
HBUSREQ <= 1'b0;
HEN <= 1'b0;
HRWN <= 1'b1;
//ADDR <= 32'h00000000;
//BYTEN <= 2'h3;
//WDATA <= 32'h00000000;
end
else if(HREADY & !AHB_Load)
begin
$display("%m Grant Get!");
AHB_Load<= 1'b1;
HEN <= 1'b1;
HRWN <= TWRITEn;
//ADDR <= TADDR;
//BYTEN <= TBYTEN;
//WDATA <= TWDATA;
end
end // HGRANT
end // CLK
end
always @(posedge HCLK) if(HGRANT & HKGrant) $display("%m Grant Kill");
endmodule
/1 
eetop公众号
创芯大讲堂
创芯人才网