日志
AHBAPB AHB_Arbiter
| |
module AHB_Arbiter(
input wire HRESETn,
input wire HCLK,
input wire [3:0] HBUSREQx,
output reg [3:0] HGRANTx,
input wire [31:0] HADDR,
input wire HREADY,
input wire HKGrant,
output reg [3:0] HMASTER
);
reg [1:0] State_A;
reg [3:0] REQi;
reg [3:0] GRANTo;
reg [3:0] GRANT_nx;
// roll the Input Request , and roll back for Output Grant next state
always @(*)
begin
case (State_A) // Roll right Roll left
2'b00: begin REQi = HBUSREQx[3:0]; GRANT_nx = GRANTo[3:0]; end
2'b01: begin REQi = {HBUSREQx[0] , HBUSREQx[3:1]}; GRANT_nx = {GRANTo[2:0], GRANTo[3]}; end
2'b10: begin REQi = {HBUSREQx[1:0], HBUSREQx[3:2]}; GRANT_nx = {GRANTo[1:0], GRANTo[3:2]}; end
2'b11: begin REQi = {HBUSREQx[2:0], HBUSREQx[3]}; GRANT_nx = {GRANTo[0] , GRANTo[3:1]}; end
default:begin REQi = HBUSREQx[3:0]; GRANT_nx = GRANTo[3:0]; end
endcase
end
// fixed arbiter
always @(*)
begin
casex(REQi)
4'bxxx1: GRANTo = 4'b0001;
4'bxx10: GRANTo = 4'b0010;
4'bx100: GRANTo = 4'b0100;
4'b1000: GRANTo = 4'b1000;
default: GRANTo = 4'b0000;
endcase
end
// GRANT the master when there is no grant
assign allowGrant = (HGRANTx == 4'h0);
always @(posedge HCLK or negedge HRESETn)
begin
if(!HRESETn) HGRANTx <= 4'h0;
else HGRANTx <= HKGrant ? 4'h0 : allowGrant ? GRANT_nx : HGRANTx;
end
// Decode when HREADY
always @(posedge HCLK or negedge HRESETn)
begin
if(!HRESETn) HMASTER <= 4'h0;
else if(HREADY)
case(HGRANTx)
4'b0001: HMASTER <= 4'h0;
4'b0010: HMASTER <= 4'h1;
4'b0100: HMASTER <= 4'h2;
4'b1000: HMASTER <= 4'h3;
default: HMASTER <= 4'h0;
endcase
end
// change inside state
always @(posedge HCLK or negedge HRESETn)
begin
if(!HRESETn) State_A <= 2'h0;
else if (HKGrant) State_A <= State_A + 1;
end
endmodule
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