# Set the current_design #

read_verilog {counter_pad.v counter.v} //读取设计文件

current_design Cnt10_PAD

link

set_operating_conditions -max slow -max_library slow -min fast -min_library fast //设置工作条件

set_wire_load_mode enclosed  //设置连线负载模型

set_wire_load_model -name tsmc18_wl10 -library slow   //设置连线负载模型

set_local_link_library {slow.db fast.db}  //设置链接库

set_max_area 0  //设置面积

set_max_fanout 5 [get_ports reset_n] //设置最大扇出

set_max_fanout 4 [get_ports clk]  //设置最大扇出

set_max_fanout 4 [get_ports in_ena] //设置最大扇出

set_max_transition 0.3 [get_ports reset_n] //设置信号翻转时间

set_max_transition 0.3 [get_ports clk]//设置信号翻转时间

set_max_transition 0.5 [get_ports in_ena]//设置信号翻转时间

create_clock [get_ports clk]  -period 10  -waveform. {0 5}//创建时钟

set_clock_latency 1  [get_clocks clk]//设置时钟源延时

set_clock_latency -source 1  [get_clocks clk]

set_clock_uncertainty -setup 0.5  [get_clocks clk]//设置时钟不确定度

set_clock_uncertainty -hold 0.4  [get_clocks clk]

set_dont_touch_network [get_clocks clk]//设置伪路径，不要约束

set_clock_transition -fall 0.3 [get_clocks clk]////设置下降沿信号翻转时间

set_clock_transition -rise 0.3 [get_clocks clk]///设置上升沿沿信号翻转时间

set_input_delay -clock clk  -max 3  [get_ports in_ena]//设置输入延时

set_output_delay -clock clk -max 4 [get_ports cnt]//设置输出延时

set_output_delay -clock clk -min 0.5 [get_ports cnt]

set_output_delay -clock clk  -max 4  [get_ports carry_ena]

set_output_delay -clock clk  -min 0.5  [get_ports carry_ena]

compile//编译

report_timing -delay max > ./reports/pad_setup_rt.rpt//报告最大时序延时

report_timing -delay min > ./reports/pad_hold_rt.rpt//报告最小时序延时

report_constraint -verbose > ./reports/pad_rc.rpt

report_qor > ./reports/pad_rq.rpt

remove_unconnected_ports -blast_buses [get_cells -hierarchical *]

set bus_inference_style. {%s[%d]}  

set bus_naming_style. {%s[%d]}

set hdlout_internal_busses true   

change_names -hierarchy -rule verilog

define_name_rules name_rule -allowed {a-z A-Z 0-9 _} -max_length 255 -type cell

define_name_rules name_rule -allowed {a-z A-Z 0-9 _[]} -max_length 255 -type net

define_name_rules name_rule -map {{"\\*cell\\*" "cell"}}

define_name_rules name_rule -case_insensitive

change_names -hierarchy -rules name_rule

write -format verilog -hier -o ./outputs/pad_counter.sv

write -format ddc -hier -o ./outputs/pad_counter.ddc

write_sdc ./outputs/pad_counter.sdc

write_sdf ./outputs/pad_counter.sdf