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XDC

已有 15 次阅读| 2022-1-10 11:18 |系统分类:芯片设计| XDC

##GTY Reference CLK

set_property PACKAGE_PIN R33   [get_ports CLK_FPGA_MGT_N      ]

set_property PACKAGE_PIN R32   [get_ports CLK_FPGA_MGT_P      ]


##SYS CLOCK  LVDS

set_property PACKAGE_PIN AT15  [get_ports FPGA_SYSCLK_P             ]

set_property PACKAGE_PIN AU15  [get_ports FPGA_SYSCLK_N             ]

set_property IOSTANDARD LVDS [get_ports FPGA_SYSCLK_P]

set_property IOSTANDARD LVDS [get_ports FPGA_SYSCLK_N]

set_property EQUALIZATION  EQ_LEVEL0 [get_ports FPGA_SYSCLK_P]

set_property EQUALIZATION  EQ_LEVEL0 [get_ports FPGA_SYSCLK_N]

set_property DIFF_TERM_ADV TERM_100  [get_ports FPGA_SYSCLK_P]

set_property DIFF_TERM_ADV TERM_100  [get_ports FPGA_SYSCLK_N]

set_property DQS_BIAS      TRUE      [get_ports FPGA_SYSCLK_P]

set_property DQS_BIAS      TRUE      [get_ports FPGA_SYSCLK_N]


##CLK SINGLE 

set_property PACKAGE_PIN G10   [get_ports TCXO_OUT_PLL              ]

set_property IOSTANDARD LVCMOS33  [get_ports TCXO_OUT_PLL              ]


set_property DRIVE 8 [get_ports BUF_ACDC_UVALM     ]

set_property SLEW SLOW [get_ports BUF_ACDC_UVALM     ]


set_property IOSTANDARD ANALOG  [get_ports RET_CURRENT_MON_N         ]


##################################################################

## SerDes   130/231

##################################################################

###CPRI BAND130

set_property LOC GTYE4_CHANNEL_X0Y15 [get_cells -hierarchical -filter {NAME =~*_CPRIPHY_TOP/u_serdes_wrap/*/port_ary[0].PHY_I/*/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST}]

set_property LOC GTYE4_CHANNEL_X0Y14 [get_cells -hierarchical -filter {NAME =~*_CPRIPHY_TOP/u_serdes_wrap/*/port_ary[1].PHY_I/*/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST}]

set_property LOC GTYE4_CHANNEL_X0Y13 [get_cells -hierarchical -filter {NAME =~*_CPRIPHY_TOP/u_serdes_wrap/*/port_ary[2].PHY_I/*/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST}]



###JESD BAND231

set_property LOC GTHE4_CHANNEL_X0Y31 [get_cells -hierarchical -filter {NAME =~*_DCIF_TOP/u_JESD204C_TOP/*/*gen_channel_container[7].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]

set_property LOC GTHE4_CHANNEL_X0Y30 [get_cells -hierarchical -filter {NAME =~*_DCIF_TOP/u_JESD204C_TOP/*/*gen_channel_container[7].*gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]

set_property LOC GTHE4_CHANNEL_X0Y29 [get_cells -hierarchical -filter {NAME =~*_DCIF_TOP/u_JESD204C_TOP/*/*gen_channel_container[7].*gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]

set_property LOC GTHE4_CHANNEL_X0Y28 [get_cells -hierarchical -filter {NAME =~*_DCIF_TOP/u_JESD204C_TOP/*/*gen_channel_container[7].*gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]



### Option 'CREATE_CLOCK'

# input jitter

set_system_jitter 0.100

#set_input_jitter UDE_ETH_RXC 0.100

#set_input_jitter TCXO_OUT_PLL 0.100

#set_input_jitter CLK_ECPRI_FPGA_MGT_P 0.100


#*******************************************************************************

# Timing constraint

#*******************************************************************************

## https://blog.csdn.net/weixin_42626447/article/details/88973430  

###https://cloud.tencent.com/developer/article/1585062


###get_pins中的-leaf选项，选中最底层

# Create clock

create_clock -period 40.000 -name UDE_ETH_RXC -waveform {0.000 20.000} [get_ports UDE_ETH_RXC]

create_clock -period 6.206 -name CLK_xxxx_FPGA_MGT_P -waveform {0.000 3.103} [get_ports CLK_ECPRI_FPGA_MGT_P]


# Create generated clock

create_generated_clock -name clk_122p88m [get_pins u_TOP/M2_SYSCTRL_REG/u_CLK_SYS/inst/mmcme4_adv_inst/CLKOUT0]

create_generated_clock -name clk_245p76m [get_pins u_TOP/M2_SYSCTRL_REG/u_CLK_SYS/inst/mmcme4_adv_inst/CLKOUT1]



#create_generated_clock -name eth0_txoutclk [get_pins -hier -filter {name=~*u_TOP/M0_CPU/u_mpsoc_ps_xxxx_xxxx/xxxx_i/xxxx/*gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]



set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets u_TOP/M2_SYScccc_REG/clk_in1] 

#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_TOP/M2_SYScccc_REG/u_CLK_cccc/clk_in1]  ##全局时钟资源；如果时钟输入引脚需要驱动不同时钟域的CMT（MMCM/PLL）模块，那么约束CLOCK_DEDICATED_ROUTE=BACKBONE是必须的；如果由普通的IO管脚驱动全局时钟资源，比如bufg或者mmcm，则CLOCK_DEDICATED_ROUTE = FALSE。

###从外部来的（接到板子上的）always语句中的敏感信号为时钟以外的外部信号，因为Vivado在处理外部时钟信号的时候会自动添加BUFG模块来去除时钟的抖动，但是其他的信号就不会这样做，这样的话在always语句的敏感信号列表中使用没有去抖动的外部信号就有可能导致系统不稳定，所以会出现这个错误。需要在IO配置文件最后添加：set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_IBUF]


#set_property CLOCK_DELAY_GROUP grp12 [get_nets {clk_245p76m clk_491p52m}]


set_property CLOCK_DELAY_GROUP grp491 [get_nets -of [get_pins u_TOP/M2_SYSCTRL_REG/u_CLK_SYS/inst/clkout2_buf/O]]

set_property CLOCK_DELAY_GROUP grp491 [get_nets -of [get_pins u_TOP/M2_SYSCTRL_REG/u_CLK_SYS/inst/clkout3_buf/O]]





#Exclusive Groups

#https://blog.csdn.net/u011729865/article/details/119959442

#set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks eth0_txoutclk] -group [get_clocks -include_generated_clocks eth0_rxoutclk]

#set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks eth1_txoutclk] -group [get_clocks -include_generated_clocks eth1_rxoutclk]


# Asynchronous group

#set_clock_groups -asynchronous -group [get_clocks TCXO_OUT_PLL] -group {clk_pl_0 clk_mii} -group [get_clocks clk_out1_mpsoc_ps_system_clk_153p6Mto250M_0] -group [get_clocks clk_out2_mpsoc_ps_system_clk_153p6Mto250M_0] -group [get_clocks clk_out3_mpsoc_ps_system_clk_153p6Mto250M_0] -group [get_clocks clk_out4_mpsoc_ps_system_clk_153p6Mto250M_0] -group eth0_rxoutclk -group eth0_txoutclk -group {clk_122p88m clk_245p76m clk_491p52m clk_30p72m}

set_clock_groups -asynchronous -group {clk_tcxo_122p88m clk_tcxo_245p76m clk_tcxo_30p72m} \

-group {clk_pl_0 clk_mii} \  

-group {clk_122p88m clk_245p76m clk_491p52m clk_30p72m} 

##-group {txoutclkpcs_out*} \

##-group {txusrclk2_i}



#set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins u_TOP/M2_SYSCTRL_REG/u_CLK_1588/inst/mmcme4_adv_inst/CLKOUT*]]

#set_false_path -from [get_clocks -of_objects [get_pins u_TOP/M2_SYSCTRL_REG/u_CLK_1588/inst/mmcme4_adv_inst/CLKOUT*]] -to [get_clocks clk_pl_0]



set_clock_groups -asynchronous -group {clk_122p88m clk_245p76m} -group {clk_pl_0} \

-group [get_clocks -of_objects [get_pins u_TOP/*_CPRIPHY_TOP/u_serdes_wrap/PHY_WRAP_ARY0[0].PHY_WRAP_I/port_ary[*].PHY_I/inst/gen_gtwizard_gtye4_top.phy_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK]] \

-group [get_clocks -of_objects [get_pins u_TOP/*_CPRIPHY_TOP/u_serdes_wrap/PHY_WRAP_ARY0[0].PHY_WRAP_I/port_ary[*].PHY_I/inst/gen_gtwizard_gtye4_top.phy_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS]] \

-group [get_clocks -of_objects [get_pins u_TOP/*_DCIF_TOP/u_JESD204C_TOP/JESD204C_TOP_i/jesd204C_PHY/inst/jesd204_phy_block_i/jesd204_phy_clocking/inst/mmcme4_adv_inst/CLKFBOUT]]





####set_max_delay 用于覆盖默认的setup（recovery）约束；set_min_delay 用于覆盖默认的hold（removal）约束，一般在约束异步信号时可以使用。跨时钟域的异步信号一般可以使用set_clock_groups或者set_false_path，但这两种约束方式将会导致跨时钟域的信号完全没有受到约束。使用set_max_delay约束可以保证两个异步时钟域的路劲延时依然受到约束，而不是高的离谱。；-datapath_only选项的使用将不考虑clock skew的影响，且不考虑hold约束，-from选项是必须的。；

set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] 2.560

set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] 2.560

set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_0] 2.560

set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0] 2.560

set_max_delay -datapath_only -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] 10.000

set_max_delay -datapath_only -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] 10.000




## BBCTRL

set_multicycle_path -setup -end -from [get_pins -filter REF_PIN_NAME==C -of [get_cells {u_TOP/*_xxxx_TOP/u_CPUIF/u_0x300/DATA_OUT_reg*}]] 4  ###REF_PIN_NAME==C CELL的pinname为C的引脚

set_multicycle_path -hold  -end -from [get_pins -filter REF_PIN_NAME==C -of [get_cells {u_TOP/*_xxxx_TOP/u_CPUIF/u_0x300/DATA_OUT_reg*}]] 3


## CFR

set_multicycle_path -setup -end -from [get_pins -filter REF_PIN_NAME==C -of [get_cells {u_TOP/*_DSP_TOP/U_CPUIF_DSP/*REG_WR_0x05A2*/DATA_OUT_reg*}]] 4

set_multicycle_path -hold  -end -from [get_pins -filter REF_PIN_NAME==C -of [get_cells {u_TOP/*_DSP_TOP/U_CPUIF_DSP/*REG_WR_0x05A2*/DATA_OUT_reg*}]] 3


######################################################################

## SPI constraint

######################################################################

###set_input_delay主要用于外部芯片向FPGA同步传输数据时，用来告诉FPGA外部进来的数据信号和时钟的相位关系；；为什么要设置70%？因为input delay是约束芯片外部的delay 情况，也就是外部约束70%，内部剩余30%的余量，因为外部的情况并不太清楚，所以估计的悲观一些，output delay原因同理。如果估计的过于乐观，那么如果都是这么设置的有可能导致两个block接上之后timing设置都不能满足timing check要求

##https://blog.csdn.net/zyn1347806/article/details/108649518

## Logic SPI#0

set_input_delay  -clock [get_clocks {clk_pl_0}] -min 3.5 [get_ports {FPGA_RFIC_SPI1_SDO}] 

set_input_delay  -clock [get_clocks {clk_pl_0}] -max 8.5 [get_ports {FPGA_RFIC_SPI1_SDO}]

set_output_delay -clock [get_clocks {clk_pl_0}] -min 1   [get_ports {FPGA_RFIC_SPI1_SDIO}]

set_output_delay -clock [get_clocks {clk_pl_0}] -max 3.5 [get_ports {FPGA_RFIC_SPI1_SDIO}]

set_output_delay -clock [get_clocks {clk_pl_0}] -min 1   [get_ports {FPGA_RFIC_SPI1_CSB}]

set_output_delay -clock [get_clocks {clk_pl_0}] -max 3.5 [get_ports {FPGA_RFIC_SPI1_CSB}]

set_output_delay -clock [get_clocks {clk_pl_0}] -min 1   [get_ports {FPGA_RFIC_SPI1_SCLK}]

set_output_delay -clock [get_clocks {clk_pl_0}] -max 3.5 [get_ports {FPGA_RFIC_SPI1_SCLK}]



### flase path & max delay

#set_false_path -to [get_cells -hierarchical -filter {NAME =~ */i_*_axi_if_top/*/i_*_syncer/*meta_reg*}]

#set_false_path -to [get_cells -hierarchical -filter {NAME =~ */i_*_SYNC*/*stretch_reg*}]

#set_false_path -to [get_cells -hierarchical -filter {NAME=~ */i*syncer/*d2_cdc_to*}]

###set_false_path -from [get_pins -hierarchical -filter {NAME =~ */i_pif_registers/i_TX_RESET_BUFFER/reset_flop_out_reg*/C }] -to [get_pins -hierarchical -filter {NAME =~ */i_pif_registers/i_pmtick_tx_clk_syncer/i_syncpls_clkout_rstsync/reset_pipe_stretch_reg*/PRE}]


# multicycle path

###set_multicycle_path -setup -end -from [get_pins -filter REF_PIN_NAME==C -of [get_cells {u_TOP/M0_CPU/u_mpsoc_ps_system_wrapper/mpsoc_ps_system_i/SYNCE_SYSTEM_TIMER/PTP_SYSTEM_TIMER_0/U0/fractional_cnt_max_reg[*]}]] 2

###set_multicycle_path -hold -end -from [get_pins -filter REF_PIN_NAME==C -of [get_cells {u_TOP/M0_CPU/u_mpsoc_ps_system_wrapper/mpsoc_ps_system_i/SYNCE_SYSTEM_TIMER/PTP_SYSTEM_TIMER_0/U0/fractional_cnt_max_reg[*]}]] 2




create_clock -period 4.069 -name CLK_SYSX8 [get_ports CLK_SYSX8]

create_clock -period 2.035 -name CLK_SYSX16 [get_ports CLK_SYSX16]

create_clock -period 10.000 -name CLK_CPU [get_ports CLK_CPU]


##set_clock_groups -asynchronous -group {CLK_SYSX8 CLK_SYSX16} 

set_clock_groups -asynchronous -group {CLK_SYSX8 CLK_SYSX16} -group {CLK_CPU} 


set_multicycle_path -setup -end -from [get_pins -filter REF_PIN_NAME==C -of [get_cells {u_CPUIF/u_0x300/DATA_OUT_reg*}]] 4

set_multicycle_path -hold  -end -from [get_pins -filter REF_PIN_NAME==C -of [get_cells {u_CPUIF/u_0x300/DATA_OUT_reg*}]] 3

set_multicycle_path -setup -end -from [get_pins -filter REF_PIN_NAME==C -of [get_cells {u_CPUIF/u_0x100/DATA_OUT_reg*}]] 4

set_multicycle_path -hold  -end -from [get_pins -filter REF_PIN_NAME==C -of [get_cells {u_CPUIF/u_0x100/DATA_OUT_reg*}]] 3


set_property  IOB true [get_ports {port_name}]

set_property  IOB true [get_cells {cell_name}]

set_property IOB TRUE [get_cells U_RUFPGA/U6_MISC_TOP/U_CPLDCTRL_V2/CPLD_10MS_reg]


##用于把时钟和驱动逻辑放在一个clock domain中。减少clock domain之间时钟线的穿越。

set_property CLOCK_LOW_FANOUT TRUE [get_nets -of [get_pins u_TOP/X1_CPRIPHY/U_SERDES_WRAP/U_CPRI_ARY[*].rxoutclk_bufg_i/O]]



##unplaced pins

https://blog.csdn.net/zhanghaijun2013/article/details/120833817

##implement

https://blog.csdn.net/zhanghaijun2013/article/details/120177596


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