/*

final

*/
module pfd_mine(
 fin,
 fout,
 up_phase,
 down_phase
);

input fin;
input fout;
output up_phase;
output down_phase;

reg dff_inst2;
reg dff_inst1;
wire wire_upphase;
wire wire_downphase;
wire wire_and_clr;
wire wire_and_clr_;

parameter  Highlevel=1'd1;
parameter  Lowlevel=1'd0;

assign wire_and_clr_=~wire_and_clr;
assign  wire_and_clr=dff_inst1&dff_inst2;
assign      up_phase=dff_inst1;
assign    down_phase=dff_inst2;

//********************************
always@(posedge fin or negedge wire_and_clr_)
begin
if (!wire_and_clr_)
 begin
 dff_inst1 = Lowlevel;
 end
else
 begin
 dff_inst1 = Highlevel;
 end
end

//******************
always@(posedge fout or negedge wire_and_clr_)
begin
if (!wire_and_clr_)
 begin
 dff_inst2 = Lowlevel;
 end
else
 begin
 dff_inst2 = Highlevel;
 end
end
//*********************

endmodule

我很欣赏的思维方式，东西很小，很有意思。