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FPGA 调试

已有 908 次阅读| 2012-8-10 09:48


    一个简单的采样电路,输入的信号sign_a,sign_b,sign_c的频率小于100Hz,大于60Hz,但是信号来的时刻不确定,刚刚开始采用以下采样方式,结果,运行到机器后,结果很不理性,不稳定,
输出波形 wave_out_1,wave_out_2,wave_out_3,wave_out_4,wave_out_5,wave_out_6竟然一片杂乱,我一头雾水,明明是以下很简单的逻辑模块竟然......
    经过思想斗争做了如下改动,
    1)输入信号先跟系统时钟同步后,在输入到采样电路.
    机器运转成功,心理非常激动,之前一个小小的疏忽,却给系统带来的大的影响,深深体会到保证系统时序稳定的重要性。
 //*******

修改前

//***********
module getdata();


input clk,rst;
input sign_a,sign_b,sign_c;

output wave_out_1,wave_out_2,wave_out_3,wave_out_4,wave_out_5,wave_out_6;

 

reg [16:1]cnt_1250;
reg clk_20k;
reg wave_out_1,wave_out_2,wave_out_3,wave_out_4,wave_out_5,wave_out_6;


//**************

always @(posedge clk or negedge rst)
begin
if(!rst)
cnt_1250<=16'd0;
else
if(cnt_1250>=16'd2499)
cnt_1250<=0;
else
cnt_1250<=cnt_1250+1;

end
//******************clk_20K


always @(posedge clk or negedge rst)

begin
if(!rst)
clk_20k<=0;
else
    if(cnt_1250>=16'd1249)
    clk_20k<=1'd0;
    else
    clk_20k<=1'd1;
     
end

////////////////////

always @(posedge clk  or negedge rst)

begin

if(!rst)

     begin
     wave_out_1<=1'd0;
     wave_out_2<=1'd0;
     wave_out_3<=1'd0;
     wave_out_4<=1'd0;
     wave_out_5<=1'd0;
     wave_out_6<=1'd0;           
     end

 

else
 
    begin
         case({sign_a,sign_b,sign_c})

          
          
         3'b110://001
                begin
                wave_out_1<=clk_20k;
                wave_out_2<=1'd0;
                wave_out_3<=1'd0;
                wave_out_4<=1'd0;
                wave_out_5<=1'd0;
                wave_out_6<=clk_20k;
            
                end

         3'b100://011
                begin
                wave_out_1<=clk_20k;
                wave_out_2<=1'd0;
                wave_out_3<=1'd0;
                wave_out_4<=clk_20k;
                wave_out_5<=1'd0;
                wave_out_6<=1'd0;
            
                end


         3'b101://010
                begin
                wave_out_1<=1'd0;
                wave_out_2<=1'd0;
                wave_out_3<=1'd0;
                wave_out_4<=clk_20k;
                wave_out_5<=clk_20k;
                wave_out_6<=1'd0;
            
                end

      
           endcase
     end
end

 


//**************

 

endmodule

 

 

 

 

修改后

//***********
module getdata();


input clk,rst;
input sign_a,sign_b,sign_c;

output wave_out_1,wave_out_2,wave_out_3,wave_out_4,wave_out_5,wave_out_6;

 

reg [16:1]cnt_1250;
reg clk_20k;
reg wave_out_1,wave_out_2,wave_out_3,wave_out_4,wave_out_5,wave_out_6;
reg sign_a_buf,sign_b_buf,sign_c_buf;

//***********

always @(posedge clk or negedge rst)
begin
     if(!rst)
        begin
           sign_a_buf<=1'd0;
           sign_b_buf<=1'd0;
           sign_c_buf<=1'd0;
        end
    else
        begin
            sign_a_buf<=sign_a;
            sign_b_buf<=sign_b;
            sign_c_buf<=sign_c;
        end
end

 


//*******************

 

 

 

//**************

always @(posedge clk or negedge rst)
begin
if(!rst)
cnt_1250<=16'd0;
else
if(cnt_1250>=16'd2499)
cnt_1250<=0;
else
cnt_1250<=cnt_1250+1;

end
//******************clk_20K


always @(posedge clk or negedge rst)

begin
if(!rst)
clk_20k<=0;
else
    if(cnt_1250>=16'd1249)
    clk_20k<=1'd0;
    else
    clk_20k<=1'd1;
     
end

////////////////////

always @(posedge clk  or negedge rst)

begin

if(!rst)

     begin
     wave_out_1<=1'd0;
     wave_out_2<=1'd0;
     wave_out_3<=1'd0;
     wave_out_4<=1'd0;
     wave_out_5<=1'd0;
     wave_out_6<=1'd0;           
     end

 

else
 
    begin
         case({sign_a_buf,sign_b_buf,sign_c_buf})

          
          
         3'b110://001
                begin
                wave_out_1<=clk_20k;
                wave_out_2<=1'd0;
                wave_out_3<=1'd0;
                wave_out_4<=1'd0;
                wave_out_5<=1'd0;
                wave_out_6<=clk_20k;
            
                end

         3'b100://011
                begin
                wave_out_1<=clk_20k;
                wave_out_2<=1'd0;
                wave_out_3<=1'd0;
                wave_out_4<=clk_20k;
                wave_out_5<=1'd0;
                wave_out_6<=1'd0;
            
                end


         3'b101://010
                begin
                wave_out_1<=1'd0;
                wave_out_2<=1'd0;
                wave_out_3<=1'd0;
                wave_out_4<=clk_20k;
                wave_out_5<=clk_20k;
                wave_out_6<=1'd0;
            
                end

      
           endcase
     end
end

 


//**************

 

endmodule

//**************

 

喜欢一句简单的话,科学有险阻,苦战能过关


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回复 shiyinjita 2012-8-16 21:59
:loveliness:

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