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check bus skew
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Question:
I have a custom cell in which a data signal is gated by an enable signal. I added arcs to my design to ensure that this enable signal is stable when the data signal arrives:set_data_check
set_data_check -from U6/DAT -to U6/EN -setup 1.0 set_data_check -from U6/DAT -to U6/EN -hold 1.0
After examining the report, I have determined that the correct checks are being performed:
Startpoint: U1 (rising edge-triggered flip-flop clocked by CLK) Endpoint: U6 (rising edge-triggered data to data check clocked by CLK) Path Group: CLK Path Type: min Point Incr Path --------------------------------------------------------------- clock CLK (rise edge) 10.00 10.00 clock network delay (propagated) 0.00 10.00 U1/CK (D_FF) 0.00 10.00 r U1/Q (D_FF) 1.40 11.40 f U6/EN (AN4) 0.00 11.40 f data arrival time 11.40 clock CLK (rise edge) 0.00 0.00 clock network delay (propagated) 0.00 0.00 U4/CK (D_FF) 0.00 0.00 r U4/Q (D_FF) 1.51 1.51 r U6/DAT (AN4) 0.00 1.51 r data check hold time 1.00 2.51 data required time 2.51 --------------------------------------------------------------- data required time 2.51 data arrival time -11.40 --------------------------------------------------------------- slack (MET) 8.90 Startpoint: U1 (rising edge-triggered flip-flop clocked by CLK) Endpoint: U6 (falling edge-triggered data to data check clocked by CLK) Path Group: CLK Path Type: max Point Incr Path --------------------------------------------------------------- clock CLK (rise edge) 0.00 0.00 clock network delay (propagated) 0.00 0.00 U1/CK (D_FF) 0.00 0.00 r U1/Q (D_FF) 1.51 1.51 r U6/EN (AN4) 0.00 1.51 r data arrival time 1.51 clock CLK (rise edge) 0.00 0.00 clock network delay (propagated) 0.00 0.00 U4/CK (D_FF) 0.00 0.00 r U4/Q (D_FF) 1.40 1.40 f U6/DAT (AN4) 0.00 1.40 f data check setup time -1.00 0.40 data required time 0.40 --------------------------------------------------------------- data required time 0.40 data arrival time -1.51 --------------------------------------------------------------- slack (VIOLATED) -1.10
I would like to add it permanently to this library cell. So, I added a non-sequential setup and hold arc to the cell with the same check value:
timing() {
related_pin : "DAT" ;
timing_type : non_seq_setup_rising ;
rise_constraint(constraint) {
values("1.000000, 1.000000", \
"1.000000, 1.000000");
}
}
timing() {
related_pin : "DAT" ;
timing_type : non_seq_hold_rising ;
rise_constraint(constraint) {
values("1.000000, 1.000000", \
"1.000000, 1.000000");
}
}When using this newly-compiled library cell, I get the same check:
Startpoint: U1 (rising edge-triggered flip-flop clocked by CLK) Endpoint: U6 (rising edge-triggered data to data check clocked by CLK) Path Group: CLK Path Type: min Point Incr Path --------------------------------------------------------------- clock CLK (rise edge) 10.00 10.00 clock network delay (propagated) 0.00 10.00 U1/CK (D_FF) 0.00 10.00 r U1/Q (D_FF) 1.40 11.40 f U6/EN (AN4) 0.00 11.40 f data arrival time 11.40 clock CLK (rise edge) 0.00 0.00 clock network delay (propagated) 0.00 0.00 U4/CK (D_FF) 0.00 0.00 r U4/Q (D_FF) 1.51 1.51 r U6/DAT (AN4) 0.00 1.51 r data check hold time 1.00 2.51 data required time 2.51 --------------------------------------------------------------- data required time 2.51 data arrival time -11.40 --------------------------------------------------------------- slack (MET) 8.90
Is there any difference between the command and the non-sequential hold library arc?set_data_check
Answer:
In the example above, the checks are effectively the same. The command simply annotates an additional data-to-data check onto the design.set_data_check
Check Conventions and Terminology
A data-to-data setup check specifies how early the constrained signal (the "-to" pin) must arrive relative to the related pin (the "-from" pin). It is specified in terms of a positive leading offset relative to the related pin; this means positive values indicate a leftward, or "leading," direction on a waveform diagram. If the constrained signal arrives too late relative to the check, it will fail. This check is shown in Figure 1:
Figure 1: Setup Data-To-Data Check
A data-to-data hold check specifies how late the constrained signal must arrive relative to the related pin. It is specified in terms of a positive trailing offset relative to the related pin; this means positive values indicate a rightward, or "trailing," direction on a waveform diagram. If the constrained signal arrives too early relative to the check, it will fail. This check is shown in Figure 2:
Figure 2: Hold Data-To-Data Check
Together, the setup and hold checks enforce a stable region around the constrained pin edge where the related pin must not toggle:
Figure 3: Setup and Hold Stability Region
In all cases, an increasingly positive check value represents tighter (more conservative) constraint behavior, and an increasingly negative check value represents more relaxed constraint behavior.
Behavioral Differences
There are some notable differences in the capabilities of the two check mechanisms.
In a library non-sequential check arc, the check value can be the result of a 1-D or 2-D table lookup rather than a single constant check value. The command only allows the application of constant check values (although this value could in theory be calculated before it is applied).set_data_check
With the command, any two data pins in the design can be specified, and the check arc will span between those two pins. The pins can be on different cells, different hierarchies, and even completely different parts of the design. In contrast, the library check arcs can only exist between two pins within the same cell.set_data_check
Note that the command should not be used on pins in the clock network. As specified explicitly in the man page, clock network pins are not supported, and undefined behavior could result.set_data_check
Simplifying Data-to-Data Hold Checks
A common source of confusion is the fact that non-sequential and data-to-data checks are inferred as zero-cycle checks. Let's say we issue a simple data-to-data hold check:
set_data_check -hold 0.123 -from U3/A1 -to U7/I
If we generate a hold-time report against U7/I, our check is such that our startpoint launches one cycle later than the endpoint:
Startpoint: FF3 (rising edge-triggered flip-flop clocked by CLK) Endpoint: U7 (falling edge-triggered data to data check clocked by CLK) Path Group: CLK Path Type: min Point Incr Path --------------------------------------------------------------- clock CLK (rise edge) 10.000 10.000 clock network delay (ideal) 0.000 10.000 FF3/CP (DFD1) 0.000 10.000 r FF3/Q (DFD1) 0.349 10.349 r U5/Z (BUFFD1) 0.083 10.432 r U6/Z (BUFFD1) 0.081 10.514 r U7/I (BUFFD1) 0.000 10.514 r data arrival time 10.514 clock CLK (rise edge) 0.000 0.000 clock network delay (ideal) 0.000 0.000 FF1/CP (DFD1) 0.000 0.000 r FF1/Q (DFD1) 0.345 0.345 r U1/ZN (INVD1) 0.029 0.374 f U2/Z (BUFFD1) 0.080 0.454 f U3/A1 (OR2D1) 0.000 0.454 f data check hold time 0.123 0.577 data required time 0.577 --------------------------------------------------------------- data required time 0.577 data arrival time -10.514 --------------------------------------------------------------- slack (MET) 9.937
Normal flop-to-flop paths in the design are inferred with a multicycle multiplier of 1. This means that setup captures a cycle later than launch, and that hold captures on the same cycle as launch. However, our check is inferred with a multicycle multiplier of 0, which pulls the capture one cycle to the left for both setup and hold checking. To understand how the multicycle multiplier affects the inference of setup/hold checks, refer to the "Setting Multicycle Paths" section of the "Timing Exceptions" chapter in the PrimeTime User Guide.
We have two ways to get the desired check. The first is to apply an additional multicycle modifier to force the hold check edges back:
set_multicycle_path -1 -hold -to U7/I
This results in the desired data-to-data hold check (as reported by ):report_timing -exceptions dominant
Startpoint: FF3 (rising edge-triggered flip-flop clocked by CLK) Endpoint: U7 (falling edge-triggered data to data check clocked by CLK) Path Group: CLK Path Type: min Point Incr Path --------------------------------------------------------------- clock CLK (rise edge) 0.000 0.000 clock network delay (ideal) 0.000 0.000 FF3/CP (DFD1) 0.000 0.000 r FF3/Q (DFD1) 0.349 0.349 r U5/Z (BUFFD1) 0.083 0.432 r U6/Z (BUFFD1) 0.081 0.514 r U7/I (BUFFD1) 0.000 0.514 r data arrival time 0.514 clock CLK (rise edge) 0.000 0.000 clock network delay (ideal) 0.000 0.000 FF1/CP (DFD1) 0.000 0.000 r FF1/Q (DFD1) 0.345 0.345 r U1/ZN (INVD1) 0.029 0.374 f U2/Z (BUFFD1) 0.080 0.454 f U3/A1 (OR2D1) 0.000 0.454 f data check hold time 0.123 0.577 data required time 0.577 --------------------------------------------------------------- data required time 0.577 data arrival time -0.514 --------------------------------------------------------------- slack (VIOLATED) -0.063 The dominant exceptions are: From To Setup Hold ------------------------------------------------------------------------------ * U7/I * cycles=-1
However, there is an easier way! We can take advantage of the fact that data-to-data zero-cycle setup checks already have their launch and capture on the same cycle. We simply rewrite the check as a data-to-data setup check and swap the pins:
set_data_check -setup 0.123 -from U7/I -to U3/A1
This gives us the desired check without any further trouble:
Startpoint: FF1 (rising edge-triggered flip-flop clocked by CLK) Endpoint: U3 (rising edge-triggered data to data check clocked by CLK) Path Group: CLK Path Type: max Point Incr Path --------------------------------------------------------------- clock CLK (rise edge) 0.000 0.000 clock network delay (ideal) 0.000 0.000 FF1/CP (DFD1) 0.000 0.000 r FF1/Q (DFD1) 0.345 0.345 r U1/ZN (INVD1) 0.029 0.374 f U2/Z (BUFFD1) 0.080 0.454 f U3/A1 (OR2D1) 0.000 0.454 f data arrival time 0.454 clock CLK (rise edge) 0.000 0.000 clock network delay (ideal) 0.000 0.000 FF3/CP (DFD1) 0.000 0.000 r FF3/Q (DFD1) 0.349 0.349 r U5/Z (BUFFD1) 0.083 0.432 r U6/Z (BUFFD1) 0.081 0.514 r U7/I (BUFFD1) 0.000 0.514 r data check setup time -0.123 0.391 data required time 0.391 --------------------------------------------------------------- data required time 0.391 data arrival time -0.454 --------------------------------------------------------------- slack (VIOLATED) -0.063
This is the data-check equivalent of swapping the sides of an inequality (A < B is the same as B > A). In fact, the primary usage model of was meant to be as setup checks applied to the design. Hold checks existed for symmetry reasons, but the resulting zero-cycle hold check behavior is much less intuitive than the zero-cycle setup check behavior. It is most straightforward if the data-to-data checks in an analysis are always specified as setup checks.set_data_check
可用方法：set_data_check；
若要设置releated pin与constrainted pin的skew，则可如下设置：
set_data_check -skew/2 -from <releatd pin> -to <constraint pin> -setup
set_data_check -skew/2 -from <releatd pin> -to <constraint pin> -hold
set_multicycle_path -1 -from <releatd pin> -to <constraint pin> -hold
因为set_multicycle_path start_point即releatd pin不能为output ports，此方法可改进为：
set_data_check -skew/2 -from <releatd pin> -to <constraint pin> -setup
set_data_check [expr clk_prd+(-skew/2)] -from <releatd pin> -to <constraint pin> -hold//此方法周期不确定时无法使用，建议使用下行方法即可
或者set_data_check -skew/2 -from <constraint pin> -to <releatd pin> -setup
若要设置releated pin与constrainted pin的skew，则可如下设置：
set_data_check -skew -from <releatd pin> -to <constraint pin> -setup
set_data_check -skew -from <releatd pin> -to <constraint pin> -hold
set_multicycle_path -1 -from <releatd pin> -to <constraint pin> -hold
因为set_multicycle_path start_point即releatd pin不能为output ports，此方法可改进为：
set_data_check -skew -from <releatd pin> -to <constraint pin> -setup
set_data_check [expr clk_prd+(-skew)] -from <releatd pin> -to <constraint pin> -hold//此方法周期不确定时无法使用，建议使用下行方法即可
或者set_data_check -skew -from <constraint pin> -to <releatd pin> -setup
另外查看该路径可以使用report_timing -to constraint pin -nworst 1000即可，加from是无效的，
另外output_delay与set_data_check会都生效，若是-nworst 1000看不到该路径，可改为-nworst 100000，直到看到为止。
注：set_data_check是一个检查约束，并不会进行优化，需出现violation时手动进行优化。
另外，两个输入端口不支持data_check；两个输出端口支持data_check；两个REGIN的内部Dpin也是支持data_check的。
set_data_check 是个啥？
set_data_check 是一条SDC 的命令，用于约束『数据-对-数据』的『建立保持』时间检查，通常被称为非时序约束 ( non-sequential constraints ), 理论上set_data_check 可以设在任意的两个data pin 上，其中一个pin 称为 constrained pin 类似于寄存器的data pin, 另一个pin 称为related pin 类似于寄存器的clock pin.
用set_data_check 约束时，-from 指定的pin 为related pin, -to 指定的pin 为constrained pin.
用set_data_check 约束的『建立保持』时间检查跟普通寄存器的『建立保持』时间检查最大的区别是：set_data_check 约束的『建立保持』时间是zero-cycle check, 即constrained signal 跟related signal 两个数据信号在同一个时钟沿被采样释放，如下图右侧所示；而传统的DFF setup check 默认是跨一个时钟周期的。
set_data_check 也分setup 跟hold:
set_data_check setup: 类似于寄存器的setup, 即related signal 翻转前，constrained signal 必须保持稳定的时间。
set_data_check hold: 类似于寄存器的hold, 即related signal 翻转后，constrained signal 必须保持稳定的时间。
set_data_check hold check 时，capture clock 同样会往前推一个cycle, 所以如果设了hold data check通常需要设一个multi_cycle 将其拉回来。
除了用set_data_check 约束『数据-对-数据』的检查之外，有的lib 里也会定义『数据-对-数据』的检查，lib 中的关键词是：
non_seq_setup_rising
non_seq_setup_falling
non_seq_hold_rising
non_seq_hold_falling
用set_data_check 约束的『数据-对-数据』检查跟lib 里定义的『数据-对-数据』有以下区别：
set_data_check 只能指定一个值，而 lib 里定义的non_seq timing check 则是一张index 为input transition 跟output load 的表格，所以更精确。
但是lib 里定义的non_seq timing check 只能在该lib cell 的leaf pin 上，而set_data_check 可以对design 中任意两个pin 进行约束。
对于C 家工具，如果既读了定义有non_seq timing check 的lib, 也设了set_data_check, 则set_data_check 优先级更高。
set_data_check 用在哪？
set_data_check 通常用于信号间的skew 约束，比如一些高速接口相关信号间的约束。摘一段：
Data checks are normally applied where there is a specific requirement of skew (either minimum of maximum) or race condition (where the order of arrival of two signals can affect output and the intention is to get one of the probable outputs by constraining one signal to come before the other) between two or more signals. These may be required where:
At the digital-analog interface within a chip where Analog signals at the analog block boundary are required in a specific order.
At the chip boundary, some asynchronous interface signals may have skew requirements.
set_data_check 在EDA 中的使用
在Innovus 或Tempus 中『数据-对-数据』检查默认是开启的，可以用如下变量控制。
对于用命令set_data_check 设置的约束，可以通过如下变量控制：
对于lib 里定义的non_seq timing check, 可以通过如下变量控制：
如果在Innovus 或Tempus 中设了如下约束，在report_timing 的时候需要加-check_type data_setup/ data_hold 来report 相应的data check:
set_data_check -from u0/D1 -to u0/D2 0.5
不像set_max_delay 会将原始的timing path 打断，set_data_check 是不会将原始timing path 打断的。
如上示例，即使在pin u0/D1 到u0/D2 上设了set_data_check 的约束，但是在timing 分析时u0/D1 不会被当做一个endpoint, 对于如上的path, timing 分析会同时做：
u0/D2 相对于 u0/D1 的data check.
到寄存器u1 的setup/hold check.
在Innovus 或Tempus 中默认其他的false path 之类的timing exception 不影响data check, 可以用如下变量控制：
timing_apply_exceptions_to_data_check_related_pin
report_analysis_coverage 会将data-to-data check 归类于：DataCheckSetup 和DataCheckHold.
本文分享自微信公众号 - 陌上风骑驴看IC（MoShangFengQiLv），作者：陌上风骑驴
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