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This article describes the recommended steps for setting up and using the SDC2SGDC feature for CDC analysis.
Design constraints available in the form of SDC or TCL can be used for SpyGlass CDC analysis. SDC2SGDC helps in reusing the set of constraints available for synthesis or timing analysis. This feature is applicable for IP (or block), SOC (or TOP) level. It is supported for flat as well as hierarchical (abstract model based) flow. Usage of this feature is the same for IP/SOC and flat/hierarchical flow.
The following table lists the SDC commands that are used for CDC analysis:
Sr. No. | SDC Command | Translated SGDC command |
1 | create_clock | clock |
2 | create_generated_clock | clock or generated_clock depending on parameters sdc_generated_clocks and enable_generated_clocks. |
3 | set_case_analysis | set_case_analysis |
4 | set_clock_groups | Used for inferring domain relation of the clocks. Also used to generate cdc_false_path commands |
5 | set_false_path | Only clock to clock false path commands are used for inferring asynchronous domain relation. All flop to flop false path commands are ignored. |
6 | set_clock_uncertainty | Used for inferring synchronous domain relation of the clocks. |
7 | set_clock_sense | clock_sense |
8 | set_disable_timing | disable_timing |
9 | set_input_delay | abstract_port |
10 | set_output_delay | output |
To specify the SDC/TCL file for a design (IP or SoC), you need to specify it in the SGDC file. For example, assume a design named ‘test’ and a sdc file as ‘test.sdc’. To specify the SDC file for the 'test' design, use the following commands in the test.sgdc file:
current_design test sdc_data –file test.sdc
Certain design teams may have defined various constraints in different SDC files. For example, consider a scenario where a sdc file called setup.sdc is used for setting up various variables, environment, mode definitions. Another sdc file called case_analysis.sdc is used for case analysis definitions for different modes and the clocks.sdc is used for the clock definitions. In addition, the timing_exceptions.sdc is used for clock groups, multi-cycle/false path commands etc. In this case, you can specify the SDC files as shown below:
current_design test sdc_data –file setup.sdc –file case_analysis.sdc –file clocks.sdc –file timing_exceptions.sdc
You can also specify multiple files as a space-separated list as shown below:
sdc_data –file setup.sdc case_analysis .sdc clocks.sdc timing_exceptions.sdc
CAUTION: Do NOT specify multiple files using separate “sdc_data” commands. Each sdc_data command is run as a stand-alone process and any variables set in one process are not maintained in the next process.
Note: The order of the files specified in the sdc_data constraint is important. For example, if variables are defined in setup.sdc, the setup.sdc must be specified before any other sdc files that use the variables. Else, many SDC related errors are reported.
To specify multiple sdc file for the same design, you can also create a single SDC file, say top.sdc, sourcing all the individual SDC files. In this case, specify the single SDC file as shown below:
current_design test sdc_data –file top.sdc
Note: The usage of various options and parameters is same for single or multiple SDC-based analysis. Therefore, details in this article are provided assuming a single SDC file.
This feature can be used in two different ways:
Single-step mode: In this mode, the SDC/TCL file is read natively and consumed by SpyGlass CDC for analysis.
Translation mode: In this mode, you first translate the SDC/TCL file by using SDC2SGDC and then review it. Modify it if any changes are required and then use the refined SGDC for SpyGlass CDC analysis. For example, add case analysis settings if the SDC has mode-independent set of constraints, modify domains of the clock to declare it as synchronous/asynchronous. Even though this is not the recommended practice, you are not restricted to use SDC only. In addition, you may like to add ‘reset’ constraints to this generated SGDC file. Note that you can specify all the resets in another SGDC file and read it along with this translated SGDC file. This would avoid modifying the generated SGDC.
Note: It is not recommended to use mix of constraints defined in SDC and SGDC file. For example, consider a scenario where a few clock groups are defined in a SDC file and another set of clocks domains are defined in the SGDC file. In this scenario, there is a high possibility of incorrect domain interpretation of the clocks. Even for case analysis setting, it is good to define it in SDC/TCL and then use. With this, approach, the SDC/TCL file can be used across the stages of design analysis. On the other hand, constraint like reset needs to be defined in the SGDC file.
In the design read setup (or global options) section of the SpyGlass project file, define the following options:
read_file –type sgdc test.sgdc
set_option sdc2sgdc yes;
# To enable translation of SDC to SGDC.
set_option sdc_generate_cfp yes;
#To enable generation of cdc_false_path commands.
set_option support_sdc_style_escaped_name yes;
#To allow non-escaped names used in SDC.
set_option sdc2sgdcfile ./<design-name>.sdc2sgdc.out;
#To specify name of the translated SGDC file.
current_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff
set_parameter sdc_domain_mode sta_scg;
#This is recommended value. This will use only set_clock_group commands for clock domain inference.
set_parameter sdc_generated_clocks yes;
#To have the generated clock definitions translated to clock constraint.
set_parameter enable_generated_clocks yes;
#To have the generated clock definitions translated in uncommented format.
Note: ALL generated clocks must be defined. If all the clock definitions are missing, the Clock_info03a rule reports unconstrained clock nets/missing clock violation messages.
With this setup, you can run SpyGlass CDC goals as shown below:
spyglass –batch –project test.prj –goal cdc/cdc_setup_check
OR
spyglass –batch –project test.prj –goal cdc/cdc_verify_struct
During the run, the SDC file is read and directly used for CDC analysis. The output is stored in the ./<design-name>.sdc2sgdc.out file.
Note: It is recommended to use the sdc2sgdcfile option and specify the name of the output SGDC file. This will help in locating the output file easily.
For this mode, the setup remains the same for the translation. However, you need to translate the SDC first, review and modify it, and then use it in the SpyGlass goal run. As explained earlier, you can add case analysis or reset constraints. To have the SDC translated, you can either run the design read step or any of the goal. For example:
spyglass –batch –project test.prj –designread
OR
spyglass –batch –project test.prj –goal cdc/cdc_setup_check
Once the run is complete, the translated SGDC would be stored in the ./<design-name>.sdc2sgdc.out file. You can review it and modify the contents of the translated SGDC as required.
Next, to use the SGDC file, modify the setup as shown below:
#read_file –type sgdc test.sgdc; #Disabling reading of the earlier SGDC file. read_file –type sgdc ./<design-name>.sdgc2sgdc.out; # Reading new SGDC file. set_option sdc2sgdc no; #Disabling translation of SDC to SGDC. OR comment out the sdc2sgdc option
With this modified setup, you can run SpyGlass CDC goals as shown below:
spyglass –batch –project test.prj –goal cdc/cdc_setup_check
OR
spyglass –batch –project test.prj –goal cdc/cdc_verify_struct
SpyGlass constraints from the translated SGDC would be used for the goal run.
Once the SDC2SGDC translation is over, you might need to understand the mapping between SDC and SGDC commands as well as clock domains inferred. Use the following rules to get the necessary details:
Rule SDC_Mapping01 – This rule generates a spreadsheet that shows the mapping between SDC commands and their corresponding command in the generated SGDC file. Following is a snapshot for reference.
Rule Domain_Matrix01 - This rule generates spreadsheet to show clock relationships and the inferred domain.
Rule Domain_Conflict01 – This rule reports conflicts found during domain inference. The severity of this rule is Error by default.
When SDC file gets read, the SDC_* rules might report multiple issues. All these issues indicate problems with the SDC file. You need to resolve these problems, such as incorrect SDC commands/options and objects not found, to ensure correct reading of the SDC.
Issues reported by the SDC_01, SDC_02/SDC_09 rules indicate pins/ports/clocks specified in the SDC but not found in the design. In addition, issues reported by the SDC_62 rule reports the presence of get_nets with generated clock commands. Note that using get_nets is not allowed when the pt option is set to no. These issues lead to missing clock definitions, not honoring clock group commands and lead to problems with SDC translation. Therefore, it is highly recommended to fix these issues before proceeding.
While dealing with SDC_02 (object not found) issues, you might come across a situation where objects specified in the SDC are visible in the SpyGlass design hierarchy. Often, these objects are declared on pins/instances present under generate block. For example, consider the SDC command given below:
create_clock –name good_clk –period 10 –waveform {0 5} [get_pins clk_box/goodmux__mux/genblk1/nice_clkumx_u0/clkmux_u0/Y]
With the default setup, SpyGlass reports the following error:
SDC_02 Error Pin: "clk_box/goodmux__mux/genblk1/nice_clkumx_u0/clkmux_u0/Y" specified in constraint file not found in design(Instance : "clk_box/goodmux__mux/genblk1 " not found)
While cross checking the design hierarchy shown by SpyGlass, you would find that the object is present and visible in the schematic. To resolve this issue, perform the following steps:
Write the following two SDC commands in a separate SDC file, such as global.sdc:
define_name_rules fix_esc –allowed ‘a-zA-Z0-9_\[\]’ –replacement_char “/”
change_names –rules fix_esc –hierarchy
Note: If constraints provided has any change_names rule applied, you need to define the same here.
Add the following parameter under current_methodology section:
#To allow names of design objects to be changed. This is helpful in reducing noise for design objects present under generate blocks as well as having name changes. Latest GuideWare or SpyGlass release L2016.06 has parameter set to value no. This is required if you are using any custom goal.set_parameter pt no;
pt
Update the input SGDC file to use the global.sdc file as below:
current_design test sdc_data –file global.sdc –file test.sdc
With this modification, re-run SpyGlass. Issues pertaining to object not found reported for objects with escape characters and generate block would be resolved. The remaining issues would definitely be correct cases. Fix it and then re-run.
Sometimes there are many issues reported by SDC_* rules for commands that are not relevant for CDC analysis. For example, issues pertaining to missing clock/pin or invalid object used in set_multicycle_path command.
While reporting object not found type of issues, the SDC_01/02 rules do not report the command name for which the issue is reported. To enable reporting of SDC commands, use the following parameter under current_methodology section:
set_parameter show_all_sdc_violations yes; #To enable reporting of all issues for the SDC.
With this parameter, the SDC_40 rule reports the SDC commands having any issue. You can use the command names to prepare a text file ignoring SDC commands not relevant to CDC analysis.
CAUTION: Use of this parameter would cause the message count to increase by many folds.
To further reduce the noise around the SDC commands which are not relevant for CDC analysis, follow the steps given below:
In a text file, say ignored_sdc_commands.txt, list all the SDC commands which are not meaningful for CDC and causing unwanted noise. List each SDC command on a separate line as shown below:
set_multicycle_path set_input_transition set_clock_transition set_clock_gating_check set_ideal_network set_max_delay ………..
Specify this text file using necessary parameter between current_methodology and current_goal commands as shown below:
current_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff set_parameter tc_ignored_commands ./ignored_sdc_commands.txt set_parameter tc_stop_parsing_ignored_commands yes; # To stop parsing of the nested/auxiliary commands present in the SDC commands which are ignored current_goal cdc/cdc_verify_struct
Once you run SpyGlass, you would observe good amount of noise reduction with these steps.
Many times designer would like to ensure that the clock group definitions are translated correctly. One of the critical and common case is discussed here.
Designers would have asynchronous relation defined between generated clocks having same source. To understand how SpyGlass handles these definitions and how the domains are associated for generated clocks, consider the structure and SDC commands given below:
create_clock –name SRC –period 10 –waveform {0 5} [get_ports src] create_generated_clock –name GENCLK1 –source [get_ports src] –divide_by 2 –master_clock [get_clocks SRC] [get_pins u1/u2/u3/Q] –add create_generated_clock –name GENCLK2 –source [get_ports src] –divide_by 4 –master_clock [get_clocks SRC] [get_pins u4/u5/u6/Q] –add set_clock_group -asynchronous -group {GENCLK1} -group {GENCLK2}
After SDC2SGDC translation, the translated SGDC would have following constraints:
clock –name “src” –domain d0 –edge {“0.00” “5.00”} –period 10 –tag SRC clock –name “top.u1.u2.u3.Q” –domain d0 –edge {“0.00” “10.00”} –period 20 –tag GENCLK1 clock –name “top.u4.u5.u6.Q” –domain d1 –edge {“0.00” “20.00”} –period 40 –tag GENCLK2 cdc_false_path –from SRC –from_type clock –to GENCLK2 –to_type clock cdc_false_path –from GENCLK2 –from_type clock –to SRC –to_type clock
With domain d0 assigned to GENCLK1, there would be no CDC analysis performed between these clocks. With cdc_false_path defined between source and generated clocks, those would be treated as synchronous/same domain clocks. At the same time, analysis between GENCLK1 and GENCLK2 would take place.
SDC2SGDC Summary – Consolidated Options and Parameters
Following is the ideal setup for SDC2SGDC:
read_file –type sgdc test.sgdc set_option sdc2sgdc yes; # To enable translation of SDC to SGDC. set_option sdc_generate_cfp yes; #To enable generation of cdc_false_path commands. set_option support_sdc_style_escaped_name yes; #To allow non-escaped names used in SDC. set_option sdc2sgdcfile ./<design-name>.sdc2sgdc.out; #To specify name of the translated SGDC file.current_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoffset_parameter sdc_domain_mode sta_scg; #This is recommended value. This will use only set_clock_group commands for clock domain inference. set_parameter pt no; #To allow names of design objects to be changed. This is helpful to reduce noise present for design objects present under generate blocks. Latest GuideWare or SpyGlass release L2016.06 has parameter pt set to value no. This is required if you are using any custom goal. set_parameter show_all_sdc_violations yes; #To enable reporting of all issues for the SDC. set_parameter tc_ignored_commands ./ignored_sdc_commands.txt set_parameter tc_stop_parsing_ignored_commands yes; # To stop parsing of the nested/auxiliary commands present in the SDC commands which are ignored set_parameter sdc_generated_clocks yes; #To have the generated clock definitions translated to clock constraint. set_parameter enable_generated_clocks yes; #To have the generated clock definitions translated in uncommented format.current_goal cdc/cdc_verify_struct
Note that the additional files, global.sdc for change name rules and ignored_sdc_commands.txt for specifying list of SDC commands are to be ignored for noise management.
For details of the parameters and options used, see the following documents:
SpyGlass CDC Rules and Parameter details: $SPYGLASS_HOME/doc/policy_guides/SpyGlass_ClockResetRules_Reference.pdf
SpyGlass options: $SPYGLASS_HOME/doc/user_guides/SpyGlass_Explorer_UserGuide.pdf
For SDC Commands: $SPYGLASS_HOME/doc/policy_guides/SpyGlass_ConstraintsRules_Reference.pdf
For SGDC Commands: $SPYGLASS_HOME/doc/policy_guides/ConsolidatedConstraintAppNote.pdf