Active Parallel Configuration

You can perform. active parallel (AP) configuration using a supported common flash interface (CFI) parallel flash memory. During AP configuration, the Altera? device is the master and the parallel flash memory is the slave. Configuration data is transferred to the Altera device on the DATA[15:0] pins. This configuration data is synchronized to the DCLK input. Configuration data is transferred at a rate of 16 bits per clock cycle. The DCLK frequency driven out by the Altera device during AP configuration is approximately 40 MHz.

Configuration Method
Using a supported common flash interface (CFI) parallel flash memory

Active Serial Configuration

The Active Serial (AS) configuration scheme is supported in the 1-bit data width (AS x1) or the 4-bit data width (AS x4).  The AS x4 scheme is supported only in Stratix? V devices. AS configuration can be performed using an Altera? serial configuration (EPCS) device or quad-serial configuration (EPCQ) device. During AS configuration, the Altera FPGA acts as the configuration master and the EPCS or EPCQ device acts as the configuration slave. The FPGA outputs the clock on the DCLK pin and receives the configuration data from the EPCS or EPCQ device on the data pin(s).

Configuration Method
Using a serial configuration (EPCS) device
Serial Configuration Devices data sheet (PDF)
Using a quad-serial configuration (EPCQ) device
Quad-serial configuration devices data sheet will be available by the end of Q2'2011

Fast Passive Parallel Configuration

To meet the continuously increasing demand for faster configuration times, Altera? devices offer fast passive parallel (FPP) configuration with different data bus widths: 8-bit data width (FPP x8), 16-bit data width (FPP x16), and 32-bit data width (FPP x32). The FPP x16 and FPP x32 schemes are supported only in Stratix? V devices.

Using an enhanced configuration (EPC) device
Altera Configuration Devices (PDF)
Enhanced Configuration Devices data sheet (PDF)
Using a microprocessor
Using a MAX? II CPLD as an external host

Passive Parallel Synchronous Configuration

A passive parallel synchronous (PPS) configuration can be performed using an intelligent host, such as a microprocessor. The PPS configuration is useful for designers who use 8-bit memory storage to store Altera? device configuration data because of its ability to receive byte-wide configuration data every eight clock cycles.

Passive Parallel Synchronous Configuration

A passive parallel synchronous (PPS) configuration can be performed using an intelligent host, such as a microprocessor. The PPS configuration is useful for designers who use 8-bit memory storage to store Altera? device configuration data because of its ability to receive byte-wide configuration data every eight clock cycles.

JTAG Configuration

The JTAG configuration scheme uses the IEEE Standard 1149.1 JTAG interface pins and supports the JAM Standard Test and Programming Language (STAPL) standard. Serial Vector File (SVF) is supported in Altera?  devices using third party programming tools. Altera devices are designed such that JTAG instructions have precedence over any device configuration mode. Therefore, JTAG configuration can take place without waiting for other configuration modes to complete. JTAG configuration can be performed using an Altera download cable or an intelligent host, such as a microprocessor.

Configuration Method
Using a download cable for in-system programmability (ISP) and prototyping

Passive Parallel Asynchronous Configuration

During PPA configuration, data is transferred from a configuration device, flash memory, or other storage device to the Altera? device on the DATA[7..0] pins. This configuration scheme is asynchronous, so control signals regulate the configuration cycle.

For more information, please refer to the configuration chapter of the relevant Altera device in the Configuration Handbook.

Configuration Method
Using an intelligent host such as microprocessor or CPLD

Passive Parallel Synchronous Configuration

A passive parallel synchronous (PPS) configuration can be performed using an intelligent host, such as a microprocessor. The PPS configuration is useful for designers who use 8-bit memory storage to store Altera? device configuration data because of its ability to receive byte-wide configuration data every eight clock cycles.

For more information, please refer to the configuration chapter of the relevant Altera device in the Configuration Handbook.

Configuration Method
Using an intelligent host such as a microprocessor

Passive Serial Configuration

Passive serial (PS) configuration can be performed using an Altera? download cable, an Altera configuration device, or an intelligent host such as a microprocessor. During PS configuration, data is transferred from a configuration device, flash memory, or other storage device to the Altera device on the DATA0 pin. This configuration data is latched into the FPGA on the rising edge of DCLK. Configuration data is transferred at a rate of one bit per clock cycle.

For more information, please refer to the configuration chapter of the relevant Altera device in the Configuration Handbook.

Configuration Methods
Using a download cable for in-system programmability (ISP) and prototyping
Using a configuration device
Altera Configuration Devices (PDF)
Enhanced Configuration Devices Data Sheet (PDF)
Using a MAX? II device as an external host
Using a microprocessor
Embedded Solutions