方法1：

module f3c(clk, reset,clk_out);
    
input clk, reset;
output clk_out;

wire clk_out;
reg clk_out1, clk_out2;

reg [1:0] count1, count2;
    
always @(posedge clk or negedge reset)
   if(!reset)
      begin
         count1 <= 0;
         clk_out1 <= 0;
      end 
  else if(count1 == 1 )
      begin
         clk_out1 <= ~clk_out1;
         count1 <= count1 + 1;
      end
  else if(count1 == 2)
      begin
        clk_out1 <= ~clk_out1;
        count1 <= 0;
      end
  else
        count1 <= count1 + 1;
  
always @(negedge clk or negedge reset)
   if(!reset)
      begin
         count2 <= 0;
         clk_out2 <= 0;
      end 
  else if(count2 == 1)
      begin
         clk_out2 <= ~clk_out2;
         count2 <= count2 + 1;
      end
  else if(count2 == 2)
      begin
        clk_out2 <= ~clk_out2;
        count2 <= 0;
      end
  else
        count2 <= count2 + 1;
          
assign clk_out = (!clk_out1 )&& (!clk_out2);         
       
endmodule

module f3c_test;

reg clk,reset;

initial
begin
reset = 1; clk = 0; 
#20 reset = 0;
#20 reset = 1;
#10000 $stop;
end

f3c f3ct(clk,reset,clk_out);

always
#50 clk = ~clk;

endmodule

方法2：

module devide_3(ref_clk,rst_n,clkout);
input  ref_clk,rst_n;
output clkout;

reg div1,div2;
reg [1:0]count;

always@(posedge ref_clk or negedge rst_n)
   begin
        if(!rst_n)
                count <= 0;
       else if(count[1:0]==2'b10)
                count <= 0;
        else
                count <= count+1;
   end
  
  
always@(posedge ref_clk or negedge rst_n)
   begin
        if(!rst_n)
                div1 <= 0;
        else if(count[1:0] == 2'b00)
                div1 <= ~div1;
        else
                div1 <= div1;
   end

always@(negedge ref_clk or negedge rst_n)
begin
        if(!rst_n)
                div2 <= 0;
        else if(count[1:0]== 2'b10)
                div2 <= ~div2;
        else
                div2 <= div2;
end

assign clkout = div1^div2;
endmodule

// test benches
module devide_t();
reg         ref_clk,rst_n;

devide_3 a1(.ref_clk(ref_clk),.rst_n(rst_n),.clkout(clkout));

initial
  begin
        ref_clk=0;
        rst_n=1;
   #100 rst_n=0;
   #300 rst_n=1;
 #10000 $stop;
  end

always #50 ref_clk=~ref_clk;
endmodule