1 结构及电气规定。

2RTL级代码设计和仿真测试平台文件准备。
3为具有存储单元的模块插入BIST(Design For test 设计)。
4为了验证设计功能,进行完全设计的动态仿真。

5设计环境设置。包括使用的设计库和其他一些环境变量。　　

6使用 Design Compiler工具,约束和综合设计,并且加入扫描链（或者JTAG）。
7使用 Design Compiler自带静态时序分析器,进行模块级静态时序分析。
8使用 Formality工具,进行 RTL级和综合后门级网表的Formal Verification。
9版图布局布线之前,使用PrimeTime工具进行整个设计的静态时序分析。
10将时序约束前标注到版图生成工具。
11 时序驱动的单元布局,时钟树插入和全局布线。
12将时钟树插入到DC的原始设计中。
13使用 Formality,对综合后网表和插入时钟树网表进行 Formal Verification。
14从全局布线后的版图中提取出估算的时间延时信息。
15将估算的时间延时信息反标注到Design Compiler或者 Primetime。　　

16在Primetime中进行静态时序分析。
17在Design Compiler中进行设计优化。
18设计的详细布线。
19从详细布线的设计中提取出实际时间延时信息。
20将提取出的实际时间延时信息反标注到Design Compiler或者Primetime中。
21使用Primetime进行版图后的静态时序分析。
22在 Design Compiler中进行设计优化（如果需要）。　　

23进行版图后带时间信息的门级仿真。
24LVS和DRC验证,然后流片。

asic (Full Chip/Sub-chip)/SOC

1.Specification

2.Architecture

3.IP implementation/Reuse and Rtl Coding

4.Simulation

5.Synthesis

6.STA

7.Floorplanning

8.Power planning

9.Placement

10.Clock Tree Synthesis (CTS)

11.Routing

12.Design Rule Check (DRC) & layout Vs Schematic (LVS)

13.Signal Integrity (SI) Analysis

14.Signoff

Step 1 Prepare an Requirement Specification

Step 2: Create an Micro-Architecture Document.

Step 3: RTL Design & Development of IP's

Step 4: Functional verification all the IP's/Check whether the RTL is freefrom Linting Errors/Analyze whether the RTL is Synthesis friendly.

Step 4a: Perform. Cycle-basedverification(Functional) to verify the protocol behaviour of the RTL

Step 4b Perform. Property Checking , to verify the RTL implementation and thespecification understanding is matching.

Step 5:  Prepare the Design Constraints file (clockdefinitions(frequency/uncertainity/jitter),I/O delay definitions, Output padload definition, Design False/Multicycle-paths) to perform. Synthesis, usuallycalled as an SDC synopsys_constraints, specific to synopsys synthesis Tool(design-compiler)

Step 6: To Perform. Synthesis for the IP, the inputs to the tool are(library file(for which synthesis needs to be targeted for, which has thefunctional/timing information available for the standard-cell library and thewire-load models for the wires based on the fanout length of the connectivity),RTL files and the Design Constraint files, So that the Synthesis tool canperform. the synthesis of the RTL files and map and optimize to meet thedesign-constraints requirements. After performing synthesis, as a part of thesynthesis flow, need to build scan-chain connectivity based on the DFT(Designfor Test) requirement, the synthesis tool (Test-compiler), builds thescan-chain.

Step7: Check whether the Design is meeting the requirements(Functional/Timing/Area/Power/DFT) after synthesis.

Step 7a: Perform. the Netlist-level PowerAnalysis, to know whether the design is meeting the power targets.

Step 7b:Perform. Gate-level Simulation with the Synthesized Netlist to check whether thedesign is meeting the functional requirements.

Step 7c: Perform. Formal-verification between RTL vsSynthesized Netlist to confirm that the synthesis Tool has not altered thefunctionality.

Step 7d Perform. STA(Static Timing Analysis) with the SDF(Standard Delay Format) fileand synthesized netlist file, to check whether the Design is meeting thetiming-requirements.

Step 7e: PerformScan-Tracing , in the DFT tool, to check whether the scan-chain is built basedon the DFT requirement.

Step 8: Once the synthesis is performed the synthesized netlistfile(Vhdl/verilog format) and the SDC (constraints file) is passed as inputfiles to the Placement and Routing Tool to perform. the back-end Actitivities.

Step 9: The next step is the Floor-planning, which means placing the IP'sbased on the connectivity,placing the memories, Create the Pad-ring, placingthe Pads(Signal/power/transfer-cells(to switch voltage domains/Cornerpads(proper accessibility for Package routing), meeting the SSNrequirements(Simultaneous Switching Noise) that when the high-speed bus isswitching that it doesn't create any noise related acitivities, creating an optimisedfloorplan, where the design meets the utilization targets of the chip.

Step 9a : Release thefloor-planned information to the package team, to perform. the packagefeasibility analysis for the pad-ring .

Step 9b: Tothe placement tool, rows are cut, blockages are created where the tool isprevented from placing the cells, then the physical placement of the cells isperformed based on the timing/area requirements.The power-grid is built to meetthe power-target's of the Chip .

Step 10: The next step is to perform. theRouting., at first the Global routing and Detailed routing, meeting theDRC(Design Rule Check) requirement as per the fabrication requirement.

Step 11: After performing Routing then the routed Verilog netlist,standard-cells LEF/DEF file is taken to the Extraction tool (to extract theparasitics(RLC) values of the chip in the SPEF format(Standard parasiticsExchange Format), and the SPEF file is generated.

Step12: Check whether the Design is meeting the requirements(Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) after Placementand Routing step.

Step 12a: Perform. the RoutedNetlist-level Power Analysis, to know whether the design has met the powertargets.

Step 12b:Perform. Gate-level Simulation with the routed Netlist to check whether thedesign is meeting the functional requirement .

Step 12c: Perform. Formal-verificationbetween RTL vs routed Netlist to confirm that the place & route Tool hasnot altered the functionality.

Step 12d Perform. STA(Static Timing Analysis) with the SPEF file and routed netlist file,to check whether the Design is meeting the timing-requirements.

Step 12e Perform. Scan-Tracing , in the DFT tool, to check whether the scan-chain isbuilt based on the DFT requirement, Peform. the Fault-coverage with the DFT tooland Generate the ATPG test-vectors.

Step 12f: Convert the ATPG test-vector to a testerunderstandable format(WGL)

Step 12g: Perform. DRC(Design Rule Check) verfication called asPhysical-verification, to confirm that the design is meeting the Fabricationrequirements.

Step 12h: PerformLVS(layout vs Spice) check, a part of the verification which takes a routednetlist converts to spice (call it SPICE-R) and convert the Synthesizednetlist(call it SPICE-S) and compare that the two are matching.

Step 12i  Perform. the ERC(Electrical Rule Checking) check, to know that the design ismeeting the ERC requirement.

Step 12j:Perform. the ESD Check, so that the proper back-to-back diodes are placed andproper guarding is there in case if we have both Analog and digital portions inour Chip. We have seperate Power and Grounds for both Digital and AnalogPortions, to reduce the Substrate-noise.

Step 12k:Perform. seperate STA(Static Timing Analysis) , to verify that theSignal-integrity of our Chip. To perform. this to the STA tool, the routednetlist and SPEF file(parasitics including coupling capacitances values), arefed to the tool. This check is important as the signal-integrity effect cancause cross-talk delay and cross-talk noise effects, and hinder in thefunctionality/timing aspects of the design.

Step 12l: Perform. IR Dropanalysis, that the Power-grid is so robust enough to with-stand the static anddynamic power-drops with in the design and the IR-drop is with-in the targetlimits.

Step 13: Once the routed design is verified for the design constraints, thennow the next step is chip-finishing activities (like metal-slotting, placingde-coupling caps).

Step 14: Now the Chip Design is ready to go to the Fabrication unit,release files which the fab can understand, GDS file.

Step 15: After the GDS file is released , perform. the LAPO check so thatthe database released to the fab is correct.

Step 16: Perform. the Package wire-bonding, which connects the chip to thePackage.