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DC synthesis script总结

已有 2870 次阅读| 2010-11-25 12:38 |个人分类:脚本

1. synthesis library设置相关:

Set_target_library, set_symbol_library, set_link_library,

Set_search_path, set_link_path

2. rtl design读入:

Read_file –format verilog *.v

Current_design $top_desing

Link

Check_desing

3. clock设置相关(clock period , uncertainty)

Create_clock –name * -period *eg. 3.8ns

Set_clock_uncertainty *eg. 0.2ns

Clock & reset network需要设置ideal & dont_touch属性:

Set_dont_touch_network *

Set_ideal_network *

另外针对clock需要设置(pre-layout阶段:未长clock tree):

Set_clock_lantency 0 *

Remove_driving_cell *

Set_drive 0 *

4.对非clock input/output port设置I/O delay

Set_input_delay –clock *à针对input port

Set_output_delay –clock *à针对output port

5. library cell设置(禁用或者指定synthesis cell):

Remove_attribute * dont_useàlibrary中有些cell是默认禁用的,需要去除其属性才能使用

Set_dont_use àdesign如果需要在synthesis时避免使用某些cell,就设置这些cell禁用

6. design rule设置:

Set_max_fanouteg. 30, set_max_transitioneg.0.8, set_max_capacitance

7. timing exception设置

Set_false_pathà如果design中存在几个clock的话,clock之间需要设置false path,避免不必要的timing check

Set_multicycle_path

8.设置clock gating celltiming check rule

For example

Set icg_dly 1.00  // gated clock cell delay assumption

Set_clock_gating_style -setup [expr $icg_dly+0.14] \

                    -hold 0 \

                    -minimum_bitwidth 3 \

                    -enhanced_min_bitwidth 6 \

                    -max_fanout 32 \

                    -sequential_cell latch \

                    -positive_edge_logic integrated \

                    -negative_edge_logic integrated \

                    -control_point before –control_signal scan_enable \

                    -num_stages 1

Insert_clock_gating

Propagate_constraints –gate_clock

Report_clock_gating -gated

9.编译:

Compile –map_effort medium –area_effort highàrtl sythesis

Compile –incremental_mapping –map_effort highànetlist optimization

10.导出synthesis report & synthesis file

1timing report

Redirect $timing_report { check_timing }

Redirect –append $timing_report { report_timing –nosplit –transition_time –nets }

Redirect –append $timing_report { report_clock –nosplit –skew –attributes }

2constraint report

Redirect $constraint_report { report_constraint –nosplit –all_violators }

2design report

Redirect $design_report { printvar [current_desing] }

Redirect –append $design_report { report_reference }

Redirect –append $design_report { report_resource }

Redirect –append $design_report { check_design }

Redirect –append $design_report { report_area –hierarchy }

3syntheiss file

Write –hierarchy –output *.db

Wirte –format verilog –hiearachy –output *_syn.v

Wirte_sdf –context verilog *.sdf

Write_sdc *.sdc -nosplit



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