Xilinx  ISE  Foundation  Tutorial for Tcl Aficionados

Volker Strumpen Austin Research Laboratory IBM  

    This section of the Xilinx ISE Foundation tutorial addresses the need for scripted design flows, which a windows interface does not offer.  We perform. (almost) the same steps than those described in the GUI based tutorial.  However, we use the Xilinx xtclsh which offers a text based interface.

    This tutorial is for the ISE Foundation Software, Version 8.2i.

    The tutorial contains the following steps:

1. Xtclsh: How to Navigate the Xilinx Tcl Shell
2. Project Execution: Tcl from Start to Finish

     References

1  Xtclsh: How to Navigate the Xilinx Tcl Shell

    Start the Xilinx Tcl Shell, called xtclsh on Linux systems.  Use the help command to navigate yourself through commands and their subcommands.  For example, try

% help project

and the xtclsh responds with

The project commands manage design files and enable processes to work on them. Sub-commands are:

new -- creates a new project
open -- opens an existing project
close -- closes the project
clean -- removes the project's temporary and automatically-generated files
... etc.

You can request help for subcommands, for example the project subcommand new:

% help project new
new <project-name> -- creates a new project named <project-name>

Since you are operating a Tcl shell, you can make use of the features provided by the Tcl language.  For example, you can assign the result of the help command to variable x:

% set x [help project new]

Subsequently, you can access the value of variable x:

% echo $x
new <project-name> -- creates a new project named <project-name>

While this example may not make a lot of sense, it should illustrate the point that the power of the xtclsh will be unleashed only when you learn to use it beyond merely executing predefined Xilinx commands, for which the GUI is perhaps even better suited.

2  Project Execution: Tcl from Start to Finish

    Four steps are required to execute a project:

1. Design entry: create the design in one of various forms, as a schematic, as a hardware description language (HDL) specification such as VHDL or Verilog, or as EDIF, which can serve as intermediate format for all of the above.
2. Create a project.
3. Configure the project.
4. Implement the design.

In the following we reuse the half-adder design that we created in the tutorial. Thus, we skip step 1, but examine each of the remaining three steps in turn.
 

2.1  Creating a Project

    Create a new working directory, say tcladder, enter the directory, and start an xtclsh.  In your xtclsh enter:

% project new tcladder.ise
tcladder.ise

to create a new project.  If you don't trust xtclsh, you may check the result by inspecting the files in the current directory using the standard Unix command ls within xtclsh:

% ls
__ISE_repository_tcladder.ise_.lock _xmsgs halfadder.edn halfadder.ucf tcladder.ise tcladder.ise_ISE_Backup

Note that the new project files are dumped into your current working directory.
Next, we can open our new project explicitly, although this is not necessary directly after generating a new project:

% project open tcladder.ise
tcladder.ise

There can be only one open project at a time.

2.2  Configuring a Project

    We are now ready to configure the project.  We begin by setting the device properties for our new project:

% project set family virtex4
Automotive CoolRunner2

sets the family to virtex4 and returns the previous setting Automotive CoolRunner2, which we simply ignore.  Before setting the device, let's check out the old value to see what to expect as a return value when assigning a new device:

% project get device
xc4vfx12

shows that the current device is an xc4vf12.  Now, set the device:

% project set device xc4vfx20
xc4vfx12

and ignore the (expected) return value.  Next, set the package:

% project set package ff672
ff672

and then the speed grade:

% project set speed -12
-12

You can examine the project properties with the project get <property> subcommand.

    As the last step of the project configuration, we register our design files with the project manager.  We reuse our half-adder from the tutorial.  If you are experimenting in a pristine working directory, copy the half-adder schematic file halfadder.sch and the UCF constraint file halfadder.ucf into your current working directory.  Then, add these files to the project using command xfile:

% xfile add halfadder.sch
true
% xfile add halfadder.ucf
true

This completes the configuration of the project.

2.3  Implementing a Design

    Implementing the design and generating the configuration file is now a matter of executing one simple command:

% process run "Generate Programming File"

which spits out a lot of information, and returns true if everything went right.  The result of the process is file halfadder.bit, that you can download to your ML405 board as described in Section 5 of the tutorial.

    The process "Generate Programming File" executes a number of steps that you may want to split, in particular if you need to debug your design.  For example, you can first implement the design, without generating the bitstream/programming file:

% process run "Implement Design"

and then generate the bitstream/programming file explicitly:

% process run "Generate Programming File"

You can split the design implementation even further into the steps you have seen in the GUI already, cf. Section 4 of the tutorial. For example, you may precede the implementation by the synthesis step:

% process run "Synthesize - XST"

If you wish to restart the implementation from scratch, use

% project clean

to remove all automatically generated design files from your working directory.  Alternatively, you can use the -force option of the process command:

% process run "Implement Design" -force rerun_all

    You should close the project before leaving xtclsh:

% project close
true
% exit

    There is a lot more to explore.  Chapter 3 of the Xilinx Development System Reference Guide lists all the commands, and contains a couple of sample scripts.

References

1. Xilinx Development System Reference Guide, Xilinx, 2006.