日志
Verilog basics
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0 Verilog History
0.1. IEEE Std 1364-1995
0.2. IEEE std 1364-2001
0.3. IEEE std 1364-2005
1. 如何加pullup
rtranif1 (port0, vdd_pull1, en);
注意：assign (pull1, pull0) port0 = en ? 1'b1 : 1'bz; // port0还是strong1
in continuous assignment, strength取决于drive signal, value也取决于drive signal
2. Verilog有两类assignment：
2.1 continuous assignment：
assign （pull1, pull0) write_en = write_en_a | write_en_b;
2.2 Procedure assignment:
always @(posedge clk or negedge resetb)
if (!resetb)
count <= 8'b0;
else
count <= count+1;
3. Net:
3.1. wire, tri: both are same, just has different application purpose
wire: driven by logic gate or continuous assignment.
tri: multi-driven (没用过，synthesizable???）
3.2. wor, wand, trior, triand: wire and/or
3.3. tri0, tri1: used for pull down/pull up (Not synthesizable)
3.4. uwire: only allow one driver, in verilog-2005
3.5. supply1/supply0: used in verdor cell library
4. verilog中的相等： ==，!= Vs ===，!==
- Logic equality: ==
- “a==b”
- Only compare when a or b is 0 or 1
- If a or b is “x”, “z”, result is always “x”/false
- tests for 1 and 0, all other will result in x
- Case equality: ===
- “a===b”
- Will compare 0/1/x/z
- When both are x or both are z, result is 1
- tests for 1, 0, z and x
- never resulting in X
Wildcard Equality: ==?, !=?
- Make few bits in RHS as don't-cares
- a =?= b
- a equals b, X and Z values act as wild cards
- may result in X if the left operand contains an x or Z
5. Verilog gate
nand #(5) (strong1, strong0) INAND0 (out, a, b)
bufif0 ar[3:0] (out, in, en); //array of 3-state buffer
pullup (strong1) p1 (neta), p2(netb);
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