日志

System Verilog Basics

已有 1555 次阅读| 2019-5-24 15:52 |个人分类:Verilog|系统分类:芯片设计| systemverilog

0. Systemverilog standard

0.1. IEEE Std 1800-2005

0.2. IEEE Std 1800-2009

0.3. IEEE Std 1800-2012

1. Packed Array and Unpacked Array

bit [7:0] B; // packed array

bit B [7:0]; // unpacked array

1.1 signed:

signed packed array: 1.1.1 viewed as a single vector is signed;

1.1.2 part-select of a packed array is unsigned

1.1.3 individual elements are unsigned

packed array: 每个array的元素都是signed

1.2 length:

packed array: 最大受计算机大小控制，至少2**16 bit

1.3 类型：

packed array: 只支持bit, logic, reg, wire

1.4 声明：

unpacked array可以像C一样： bit A [4][8]; 等价于 bit A [3:0][7:0];

1.5 system task for array:

$left, $right, $low, $high, $increment, $dimensions

$dimensions(A): 返回所有的维度，包括packed, unpacked. 例如： bit p7:0] A [4][5], 返回值是3

$unpacked_dimensions(A): 返回unpacked的维度：上面的例子返回值是2

2. DPI

2.1 使用DPI调用标准C函数getenv获取系统变量：

module top;

import "DPI-C" function string getenv(input string env_name);

string HOME;

initial HOME = getenv("HOME");

          endmodule

    2.2 普通的DPI
          sv文件：
          // First we must import the functions' declarations whose implementations are done in C

import "DPI-C" function void compute_bit(input bit i_value, output bit result);

import "DPI-C" function bit get_bit(input bit i_value);

export "DPI-C" function write();
          function void write(int address, bit data);
       get_bit(data); // Arguments passed by copy
          endfunction

          ...

         c文件：
         //include the SystemVerilog DPI header file

#include "svdpi.h"
extern void write(int, int); // Imported from SystemVerilog

void compute_bit(const svBit i_value, svBit* result) {

*result = transform_svBit(i_value);

}

svBit get_bit(const svBit i_value) {

svBit result; result = transform_svBit(i_value);

return result;

}

svBit transform_svBit(const svBit in) {

return !in;

}

2.3 type map between sv and c

C INPUT TYPE	C OUTPUT TYPE
byte	char	char*
shortint	short int	short int*
int	int	int*
longint	long int	long int*
real	double	double*
shortreal	float	float*
chandle	const void*	void*
string	const char*	char**
string[n]	const char*	char**
bit	svBit	svBit*
logic / reg	svLogic	svLogic*
bit[N:0]	const svBitVec32*	svBitVec32*
logic[N:0] reg[N:0]	const svLogicVec32*	svLogicVec32*
open array []	const svOpenArrayHandle	svOpenArrayHandle

2.4 vcs 使用C file

vcs -full64 -sverilog counter.sv counter7.c

3. CRV
    3.0 CRV: constrained random verification (Constraint Random stimulus generation)
          Combinational constraint : In ethernet, 13 & 14 th bytes should be equal to payload length.
          Sequential constraint: If request comes, then acknowledgement should be given between 4th to 10th cycles.
SV doesn't support it directly
Verilog CRV: int: $random (generate range: MIN + {$random} % (MAX - MIN ))
                             确定顺序的random, 否则没法恢复failure: $random(seed) (缺省的seed默认是0）
                                    每一次调用$random, 它会返回一个random value 和一个新的seed (seed是inout port)
                             randc int: have to use loop to make sure new generation is not repeated.
                             real: sgn = $random; exp = $random; man = $random; r_num = $bitstoreal({sgn,exp,man});
                   $random, $dist_chi_square, $dist_erlang, $dist_exponential, $dist_normal, $dist_poisson, $dist_t, $dist_uniform
                   In Verilog95, each simulator has its own random generator algorithm
                   In Verilog 2001, each simulator has to use same algorithm for randomization, so random sequences are same with same seed. (But due to race condition, random sequence may be different in different simulator)
      SV CRV: Constraints: rand/randc variable, foreach array, set membership, inline constraint, rand case, rand sequence,
conditional constraint, implication constraint
   Randomization:
                                          1. random function
                                          2. constrained and unconstrained randomization
                                          3. uniform distribution
                                          4. weighted distribution
                                          5. weighted range
                                          6. weighted case
                                          7. pre randomization/post randomization
                                              子类中如果没有pre/post_randomization, 会自动调用super.pre/post_randomization
                                          8. declaration of random variable：
                                                      支持Fixed arrays, dynamic arrays, associative arrays and queues
                                                      randc: 支持bit, enumerated, 最多支持8 bit （VCS好像是16bit???)
                                                                在new() 或constraint改变时，permutation sequence就确定了
                                                       obj.Var1.rand_mode(0); // Var1 will become State variable
                                                       obj.Var1.rand_mode(1); // // Var1 will become random variable
                                                          //rand_mode() also can used as function, it will return active status for that variable
                                                          // if var is static, rand_mode() only have effect on object
                                                          // var is not declared as rand, still can use randomize(var) to randomize
                                                       randomize(null) // checker的用法：不会randomize, 只是solve constraints
                                          9. non repeating sequence
                       Dynamic constraints:
                                          1. inline constraints
                                          2. guarded constraints
                                          3. disabling/enabling constraints
                                          4. disabling/enabling random variables
                                          5. overriding of constraint blocks
                       Random Stability : Thread stability, object stability and manual seeding
    3.1 constraint block 会被子类继承，如果同名，则会overwrite
          child_object is type-casted to base_object
                  3.1.1 如果constraint同名：base_object.randomize会使用child_object的constranint
                  3.1.2 如果constraint不同名：base_object.randomize会使用base和child的constraint共同作用
                  3.1.3 使用obj.constraint_mode(0)或obj.constraint_mode(1)可以关闭或打开所有的constraint block
                          使用obj.constraint_block_name.constraint_mode(0/1)可以关闭或打开指定的constraint block
                          if (obj.constraint_block_name.constraint_mode())的用法：返回该constraint block是否active
    3.2 inline constraint: randomize() {....}
         增加了constraint，会和原有的constraint一起作用
    3.3 global constraint: SV允许不同对象的variable出现在同一个constraint block中
              class parent;
            rand child child_obj;
              rand int Var2;
              constraint global_c { Var2 < child_obj.Var1 ;}
                       //global constraint, obj.randomize会将var2，child_obj.var2一起randomize
    3.4 external constraint
         class Base {
            constraint range
         }
         ...
         constraint Base::range { Var < 100; Var > 0;}
    3.5 constraint 不支持protect, local
    3.6 static constraint: control mode会被所有的该class的object共享
    3.7 constraint expression：使用->, dist, inside, [...], !(var insde ...), if..., if...else...
          3.7.1 Var dist { 10 := 1; 20 := 2 ; [30:32] := 2 }
                              //probability of Var is equal to 10,20,30,31 and 32 is in the ratio of 1,2,2,2,2
          3.7.2 :/ equally distributed for each element in that group
                    Var dist { 10 := 1; 20 := 2 ; [30:32] :/ 2 }
                             // probability of Var is equal to 10,20,30,31,32 is in the ration of 1,2,2/3,2/3,2/3
    3.8 constraint solve的顺序控制
          3.8.1 constraint c1 {a==0->b==0;}