日志

PLI acc_set_value()

已有 1842 次阅读| 2014-8-22 09:17 |个人分类:verification

acc_set_value()

Synopsis:

Set and propagate a value on a reg, variable, user-defined system function or a sequential UDP; procedurally assign a reg or variable; force a reg, variable, or net.

Syntax:

acc_set_value(object_handle, value_p, delay_p)

acc_set_value() shall be used to perform. a procedural continuous assignment of a value to a reg or variable or to deassign the reg or variable. This shall be the same functionality as the procedural assign and deassign keywords in the verilog hdl.

acc_set_value() shall also be used to perform. a precedural force of a value onto a reg, variable or net, or to release the reg, variable or net. This shall be the same functionality as the procedural force and release keywords in the Verilog HDL.

typedef struct t_setval_delay

{

s_acc_time time;

PLI_INT32 model;

} s_setval_delay, *p_setval_delay;

model: accNoDelay, accInertialDelay, accTransportDelay, accpureTransportDelay

typedef struct t_setval_value

{

PLI_INT32 format;

union

{

PLI_BYTE8 *str;