I have a feedthrough in my circuit, and the netlist is showing an assign statement for this feedthrough.

我的电路设计中有端口直接连接，综合后网表中使用assign语句用于此连接。How can I remove the assign statement from the netlist?;我如何去除网表中的assign语句？Answer:回答：The two most common reasons for assign statements to appear in a gate-level netlist are两个最可能的原因会造成在门级网表中出现assign语句：(1) there are feedthroughs that connect multiple ports on a single net or一条网络上连接多个端口，或者(2) the netlist contains three-state elements网表中包括三态元素。Feedthrough Nets直接连接网络hdl Compiler creates assign statements in the design when two ports are connected without logic between them. If a feedthrough has an output port connected to an input port without any logic in between, it causes Design Compiler to add the assign statement in the netlist. Design Compiler is unable to represent such connections without using nonstructural artifacts such as the assign statement.当设计中两个端口之间没有逻辑直接相连时，HDL编译器会用assign语句。如果从输入端口到输出端口的连接中间没有逻辑，DC编译器会在网表中加入assign语句。不用assign语句，DC将不会表达这种连接。To fix this problem, you need to add logic to the design to correctly represent the otherwise unrepresentable connections. To fix the feedthrough in the design, use this command before compile:要修复此问题，你需要增加逻辑正确表达这种连接。要修复设计中端口直接连接，在编译前使用如下命令：set_fix_multiple_port_nets -all -buffer_constantsDesign Compiler will then insert logic into the design to prevent ports from being connected to the same net.DC编译器会插入逻辑以避免设计中多个端口连接到同一个网络。If the net has a dont_touch attribute on it, Design Compiler is not allowed to insert logic between the input and output port connections, and the assign statement will remain in your netlist.如果此网络具有dont_touch属性，DC编译器将不被允许在输入输出端口连接中间插入逻辑，assign语句还会存在于网表中。You can correct this situation in the following ways:你可以使用下面方法修复：1. Remove the dont_touch attribute.  去除dont_touch属性2. Manually insert a buffer on the net between the input and output ports to prevent the assign statement.  在输入端口和输出端口间手动插入一个buffer来避免assign语句。Three-State Elements三态元素To avoid getting assign statements with three-state elements, set the verilogout_no_tri variable to true before writing out the netlist. Also, check that verilogout_equation is set to false.要避免有三态元素引起的assign语句，在写出网表文件之前，设定verilogout_no_tri变量为true，且检查变量verilogout_equation设定为false。verilogout_no_tri = trueverilogout_equation = falseYou can read in your compiled .db file, set the verilogout variables, and then write out the netlist. (The verilogout_equation and verilogout_no_tri variables determine the Verilog output with the write -f verilog -hier -o command.) The verilogout_equation and verilogout_no_tri variables do notaffect the compile process.你可以读入你的编译后的.db文件，设定verilogout变量，然后写出网表文件。（变量verilogout_no_tri和verilogout_equation与命令write -f verilog -hier -o一起决定了verilog的输出。）变量verilogout_no_tri和verilogout_equation不影响编译过程。To see whether the settings help eliminate the assign statements, set the variables and then write the netlist. Here is a small example of the steps required to do this in dcsh mode:要看这些设定是否帮助消除了assign语句，可以设定这些变量然后写出网表。这里提供一个dcsh格式的例子。verilogout_equation = falseverilogout_no_tri = trueread -f db your_compiled_file.dblist verilogout_equationlist verilogout_no_triwrite -f verilog -hierarchy -o netlist.vwrite -f db -hierarchy -o netlist.db2010年12月6日补充：当使用上述方法去除assign后，写出的网表文件中还是包含assign语句。使用report_comile_options命令来报告每一个design的编译选项，发现只有top的具有fix_multiple_port_nets选项。而我编译时没有使用ungroup_all选项，分析应该是编译时只是对顶层design去除了assign语句，而其它层次的design中依然保留有assign语句。解决办法：编译时使用-ungroup_all选项compile -ungroup_all2010年12月17日补充：12月6日的补充有问题。用report_compile_options命令只会显示top设计有没有fix_multiple_port_nets选项。如果有此选项，表示其整个设计的hierarchy都会在编译时fix_multiple_port_nets。所以，assign出现的原因并不是有些sub-level design没有fix_multiple_port_nets属性造成的。我也查找排除了dont_touch属性而导致编译器不能去除assign语句。发现使用change_names -hier -rules verilog可以去除assign语句。分析应该是verilog命名规则中两个选项起的作用：equal_ports_nets: trueinout_ports_equal_nets: true