SV history 2018-08-30

1. IEEE Std 1800-2005 2. IEEE Std 1800-2009 3. IEEE Std 1800-2012

(304)次阅读|(0)个评论

Verilog history 2018-08-30

1.  IEEE Std 1364-1995 2. IEEE std 1364-2001 3. IEEE std 1364-2005

(297)次阅读|(0)个评论

verilog UDP 2018-08-30

1. combinational UDP primitive tsmc_mux (q, do, d1, s);   output q;   input do, d1, s;   table  //d0, ...

(456)次阅读|(0)个评论

verilog gate 2018-08-30

nand #(5) (strong1, strong0) INAND0 (out, a, b) //array of 3-state buffer bufif0 ar (out, in, en); pullup (strong1) p1 ...

(241)次阅读|(0)个评论

Verilog Net 2018-08-30

Net: 1. wire, tri: both are same, just has different application purpose          ...

(268)次阅读|(0)个评论

各种UVM agent 2018-08-29

一般interface protocol把component分为master, slave     Master: 发起transaction     slave： 对transaction产生response 从是否 ...

(400)次阅读|(0)个评论

查看更多