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Dynamic Amplifier in Pipelined ADC

已有 1001 次阅读| 2015-7-8 10:53

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[03] B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7 mW 11b 250 MS/s 2-times interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2880–2887, Dec. 2012.

[04] S.-H. W. Chiang, H. Sun, and B. Razavi, “A 10-bit 800-MHz 19-mW CMOS ADC,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 935–949, Apr. 2014.

[05] F. van der Goes, C. Ward, S. Astgimath, H. Yan, J. Riley, J. Mulder, S. Wang, and K. Bult, “A 1.5 mW 68 dB SNDR 80 MS/s interleaved SAR-assisted pipelined ADC in 28 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp.200–201.

[06] J. Lin, D. Paik, S. Lee, M. Miyahara, and A. Matsuzawa, “A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sept. 2013.

[07] Lin, J.; Paik, D.; Seungjong Lee; Miyahara, M.; Matsuzawa, A.,An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers, Solid-State Circuits, IEEE Journal of Year: 2015, Volume: 50, Issue: 6 Pages: 1399 - 1411