module dinout(din,z,clk,dout,dinout);
 
    input[7:0] din;
    input z;
    input clk;
    output[7:0] dout;
    inout[7:0] dinout;

    reg[7:0] dout;
    reg[7:0] din_reg;

assign dinout=(!z)? din_reg : 8'bz;

always @(posedge clk)
    begin
    if(!z)
        din_reg = din ;
    else
        dout=dinout;
end

endmodule
--------------------------------
对应测试代码
`timescale   1ns/100ps

module dinouttest();
   
reg[7:0] din;
reg z;
reg clk;
wire[7:0] dout;
wire[7:0] dinout;
integer i;

dinout uut(.din(din),.z(z),.clk(clk),.dout(dout),.dinout(dinout));

always #10 clk = ~clk;
initial begin
    din = 0;
    z=0;
    clk=0;
    #200 din=10;
    for(i=0;i<10;i=i+1)
    #20 din = din + 1;
//
    z=1;
    for(i=0;i<10;i=i+1)
    #20 din = din + 2;
//
end

endmodule