学习SystemVerilog（一）——不学习它的理由

     想要学习SystemVerilog已经很久了。曾经尝试通过Accellera网站上给出的LRM学习，怎奈内容众多，找不出入手点和重点，只能望而却步。虽然手头有三本SystemVerilog方面的书：《SVA应用指南》，《SystemVerilog验证方法学》和《高级验证方法学》，但是难成系统。第一本只给出了SystemVerilog在断言方面的应用，详细实用但是不全面；第二本给出了SystemVerilog在验证领域的应用，详细全面但是过于高级而不实用，很难作为入门教材；第三本也给出了验证领域的应用，详细但是不够全面，也有高级而不实用的问题。 riple

    十一放假前，从图书馆借来了两本书：SystemVerilog for Design 和SystemVerilog for Verification。利用放假的“娱余时间”通读了两本书的前言部分和前一本书的各个章节。通过读这两本书的前言部分，我对SystemVerilog有了一些整体的认识；通过读第一本书的各个章节，我对SystemVerilog的细节有了一些初步和不成熟的认识。 riple

    随着这些认识而来的是两种相反但是不矛盾的想法：不应该学SystemVerilog和应该学SystemVerilog。 riple

    现在来说说为什么不该学SystemVerilog。 riple

    从Verilog到SystemVerilog的发展过程来看，两种语言都有其产生的必要性。Verilog在上世纪80年代中期产生，解决了当时一万门以上设计面临的种种问题，Verilog的产生带来了门级设计到RTL级设计的变革，接下来的近20年，随着设计规模的扩大，Verilog也在不断的演变和扩展，但是抽象层次始终徘徊在RTL级别；进入90年代以后，Verilog较弱的验证能力逐渐显露出来，而Verilog的几次标准化过程都没能解决这一问题，在验证领域各种新的语言不断出现以代替Verilog；90年代后期，一个叫Co-Design的公司尝试扩展Verilog，增强其更高抽象级别的描述能力和用于的验证能力，这一工作产生了我们现在看到的SystemVerilog——HDL & HVL。 riple

    从我们当前的设计需要看，我们的设计规模是否达到了RTL抽象级别不能描述的程度？对于我这样的FPGA设计者来说（我相信看我博客的人大多是FPGA设计者），工作中使用的芯片资源不超过6000个LE，以一个LE等价于12个门电路来计算（谁说的来哉？），设计规模不过72000门。Verilog的设计描述能力足以应对我的日常工作。即使我的下一个项目规模是当前项目的10倍，我所做的工作不过是规划10个当前项目大小的模块，然后用近似10倍的工作量完成10个模块的编码，每个模块的设计仍然可以用Verilog完成。 riple

    虽然SystemVerilog提供了更高级别的抽象层次描述能力，但是目前的综合工具仍然不能支持其简单和直接的实现，还是需要人工逐级细化到RTL级别才能交给综合工具。只有ESL工具的进一步演化才能解决高层次抽象级别描述的可综合问题，而不是SystemVerilog。SystemVerilog是这一过程中可选的一种描述语言。 riple

    第一个认识是在阅读这两本书前言的过程中思考上述问题得到的：我们现在的设计规模虽然很大，但是我们能够人工实现的设计量与Verilog最初产生时的设计能力相比，仍然没有超出Verilog的设计能力，仍然是RTL级别。（这当然不是原书作者的观点，而且我得到的认识也不只这一点，其他的认识与这一点正好相反，放在下一篇。） riple

    通读完了SystemVerilog for Design的各个章节，我最深刻的感受是自己对Verilog语言掌握得还很不够。毕竟，Verilog是SystemVerilog的基础，而我的基础又是很差的，只够应付当前工作的需要。 riple

    这本书中提到的对Verilog的扩展和改进的大多数内容虽然很吸引人，虽然很有道理，在实际应用中也确实方便和准确了些，但是只不过是方便和准确了“一些”而已。从语言设计者的角度来说，在SystemVerilog中改进Verilog的不足是必要的，但是从语言使用者的角度来说，这些改进不是根本性的，也不是采用SystemVerilog的决定性因素。从这些内容来看，不学SystemVerilog也可以设计好数字电路。（尽管如此，这本书的另外一些内容却给出了学习SystemVerilog的必要性，这些内容我放在下一篇里。） riple

    第二个认识：对于刚刚进入逻辑设计领域的设计者来说，从工作出发，学好Verilog是必要的，学习SystemVerilog是要以学好Verilog为基础的，在Verilog的掌握和使用尚不成熟时，就强学强记SystemVerilog的高级功能是不切实际的，甚至可以说是好高骛远。 riple

    下面是从SystemVerilog LRM中摘抄的一段，给出了SystemVerilog对Verilog的所有扩展和增强。内容显然太丰富了些，更适合对SystemVerilog有了全面而深入认识的人士（比如语言的设计者），从归纳和总结的角度阅读，对于我这样基础薄弱的初学者来说，太具震慑力了些。 riple

SystemVerilog adds extended and new constructs to Verilog-2001, including:
— Extensions to data types for better encapsulation and compactness of code and for tighter specification
    — C data types: int, typedef, struct, union, enum
    — other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety
    — dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays including automatic memory management freeing users from de-allocation issues
    — dynamic casting and bit-stream casting
    — Automatic/static specification on a per variable instance basis
— Extended operators for concise description
    — Wild equality and inequality
    — built-in methods to extend the language
    — operator overloading
    — streaming operators
    — set membership
— Extended procedural statements
    — pattern matching on selection statements for use with tagged unions
    — enhanced loop statements plus the foreach statement
    — C like jump statements: return, break, continue
    — final blocks that executes at the end of simulation (inverse of initial)
    — extended event control and sequence events
— Enhanced process control
    — Extensions to always blocks to include synthesis consistent simulation semantics
    — Extensions to fork…join to model pipelines and for enhanced process control
    — Fine-grain process control
— Enhanced tasks and functions
    — C like void functions
    — pass by reference
    — default arguments
    — pass by name
    — optional arguments
    — import/export functions for DPI (Direct Programming Interface)
— Classes: Object-Oriented mechanism that provides abstraction, encapsulation, and safe pointer capabilities
— Automated testbench support with random constraints
— Interprocess communication synchronization
    — semaphores
    — mailboxes
    — event extensions, event variables, and event sequencing
— Clarification and extension of the scheduling semantics
— Cycle-Based Functionality: Clocking blocks and cycle-based attributes that help reduce development, ease maintainability, and promote reusability:
    — cycle-based signal drives and samples
    — synchronous samples
    — race-free program context
— Assertion mechanism for verifying design intent and functional coverage intent.
    — property and sequence declarations
    — assertions and Coverage statements with action blocks
— Extended hierarchy support
    — packages for declaration encapsulation with import for controlled access
    — compilation-unit scope nested modules and extern modules for separate compilation support
    — extension of port declarations to support interfaces, events, and variables.
    — $root to provide unambiguous access using hierarchical references
— Interfaces to encapsulate communication and facilitate “Communication Oriented” design
— Functional coverage
— Direct Programming Interface (DPI) for clean, efficient interoperation with other languages (C provided)
— Assertion API
— Coverage API
— Data Read API
— VPI extensions for SystemVerilog constructs
— Concurrent assertion formal semantics

学习SystemVerilog（二）——学习它的理由

学习SystemVerilog的理由也很多，我在阅读SystemVerilog for Design 和 SystemVerilog for Verification两本书前言的过程中，总结出了SystemVerilog在以下几个方面对Verilog的增强： riple

    更清晰、准确、简洁的硬件描述能力——Design。 在上一篇关于学习SystemVerilog的文章中，我不建议入门级的数字电路设计工程师学习SystemVerilog，原因是使用Verilog足以完成我们绝大多数工作。从提高代码的可读性和易维护性角度来看，使用SystemVerilog有助于提高工作效率。 riple

    编写受控随机的、分层的、可重用的测试平台的能力——Test。Verilog编写测试平台的能力就相当于采用最基本的C语言结构编程，而采用SystemVerilog编写测试平台则相当于采用C++按照面向对象的思想编程。 riple

    在设计描述和测试平台中添加断言的能力——Assertion。断言这个工具，在软件开发中早就广泛应用了。在单元测试、集成测试和功能覆盖率评估中，断言都是一个很强大的工具。 riple

    更高抽象层次的系统描述能力——Architectural Modeling。OOP、Dynamic Threads、Interprocess Communication、行为级和事物级的描述能力，从名称上看来确实高级。 riple

    使用SystemVerilog的最大好处是，上述所有特性都统一于同一种语言环境下。从系统架构设计者到底层实现设计者到验证工程师都采用同一种语言，设计过程中团队之间的交流更加准确和方便，提高了设计效率。 riple

    上述四个方面中的后三个，都是我这样的FPGA设计工程师不曾涉猎过的领域，对于大家是否应该学习SystemVerilog在这三个方面的特性，我没有发言权。需要说明的是，现在在这三个领域都有相应的较成熟的工具，尽管难以统一。大胆猜测一下，未来的发展趋势应该是SystemVerilog一统天下，因为它在这三个方面从已经成熟的工具中继承了很多，也得到了众多EDA厂商的大力支持。 riple

    对于我自己的工作来说，采用新的设计语言特性不是十分急迫，读懂示例还是需要学习新特性的；断言和系统建模两个方面是我感兴趣的领域，学到的东西也能更快地应用到我的工作中；编写简单的测试平台也是我的工作内容之一，也需要学习一下。 riple

     学习语法和使用语言是两个不同的层次。只有把语言用起来，才能真正掌握这门语言；而语法的学习，只有在语言的使用过程中才能获得更加具体形象的认识，否则学到的只是只言片语，很难融会贯通。学习使用SystemVerilog语言的方法，也就是学习一种方法学，从SystemVerilog的两个主要组成部分看来，方法学可以分为以下两大类： riple

    设计方法学：即使在SystemVerilog for Design这本书中也没有明确给出一种方法学，只是在倒数第二章给出了采用SystemVerilog语言特性进行设计描述的实例，从中应该可以总结出一套不甚完善的设计方法学。此外，《SVA使用指南》可以算作断言在设计过程中使用的方法学。 riple

    验证方法学：在验证方面的方法学相对成熟得多。SystemVerilog for Verification这本书给出了一套简单、实用的方法学，适合入门阅读，算是初级方法学；《VMM for SystemVerilog》和《高级验证方法学》则如名称所示，是高级方法学，不适合一上手就阅读。 riple

    以下文字节选自Stuart Sutherland发表在EEdesign, May 23, 2003上的一篇文章：An Overview of SystemVerilog 3.1。这篇文章可以说是SystemVerilog的入门必读文章。下面两段文字叙述了SystemVerilog产生的原因和发展过程。 riple

A problem that needed solving. For many years, the behavioral coding features of Verilog, plus a few extras such as display statements and simulation control, gave Verilog-based design engineers all they needed to both model hardware and to define a testbench to verify the model.

As design sizes have increased, however, the number of lines of RTL code required to represent the design have increased dramatically. Even more significant is the increase in the amount of verification code required to test these very large designs. While modeling large designs and verification routines in traditional RT-level HDLs is still possible, the amount of coding far exceeds what can be accomplished in a reasonable amount of time.

To address these problems, new design languages such as SystemC were created that could model full systems at a much higher level of abstraction, using fewer lines of code. Proprietary Hardware Verification Languages (HVLs) such as Verisity's e and Synopsys' Vera were created to more concisely describe complex verification routines (Note: company and product names are trademarked names of their respective companies). These proprietary languages solve a need, but at the cost of requiring engineering teams to work with multiple languages, and often at the expense of simulation performance.

The SystemVerilog standard currently being defined by Accellera takes a different approach to solving the design and verification needs of today's multi-million gate designs. Rather than re-invent the wheel with new languages, Accellera — the combined VHDL International and Open Verilog International organizations — has defined a set of high-level extensions to the IEEE 1364 Verilog-2001 language.

The definition of the SystemVerilog 3.1 standard has been completed and is expected to be released in June of this year. Accellera plans to donate the SystemVerilog extensions to the IEEE 1364 Verilog Standards Group, where it is anticipated that the extensions will become part of the next generation of the IEEE 1364 Verilog standard.

SystemVerilog's roots. Accellera chose not to concoct these SystemVerilog enhancements to Verilog from scratch. That would have required re-inventing the wheel and creating a standard based on unproven, untested syntax and semantics. Instead, Accellera relied on donations of technology from a number of companies. These donations include high-level modeling constructs from the Superlog language developed by Co-Design, testbench constructs from the Open Vera language and VCS DirectC interface technology donated by Synopsys, and assertions work from several companies, including, to name just a few, OVA from Verplex, ForSpec from Intel, Sugar (renamed PSL) from IBM, and OVA from Synopsys.

Over the past two years, the Accellera SystemVerilog committee and subcommittees have met two to four times each month to standardize these donations. Members of the SystemVerilog committee include experts in simulation engines, synthesis compilers, verification methodologies, members of the IEEE 1364 Verilog Standards Group, and senior design and verification engineers.

How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 1

How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 2