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This proven reference flow was validated using the ARM SMIC 40nm multiple channel standard cell library, Power Management Kit, memory compiler, SMIC in-house PLL and IO to illustrate a power-gating design. In addition, the reference flow leverages Unified Power Format (UPF), an IEEE standard for defining low power design intended to improve the way complex System-on-Chip (SoC) designs are implemented and verified.
SMIC and Synopsys’ collaboration has enabled IC designers to accelerate their designs into manufacturing, with a flexible, lower-risk environment and faster time-to-market with SMIC’s 40nm process technology.
SMIC-Synopsys Reference Flow 5.0 highlights:ARM SMIC 40LL library R2G design flow | |
Advanced SMIC 40nm design rule support | |
All scripts are compatible with the Synopsys Lynx Design System | |
Chip-level Low Power UPF design | |
Multi-VT libraries for leakage reduction optimization | |
Multi-channel libraries for leakage reduction optimization | |
Gate Array ECO flow |
Design flow scripts | |
Technology and library preparation scripts | |
Sample test cases, one block level and one low power chip-level design | |
Flow setup and execution manual |
Most importantly, we have trained experts ready to support and offer you professional advice to bring your design to high-quality sign-off GDSII.
If you would like to know more about the SMIC-Synopsys Reference Flow 5.0, please contact your SMIC account manager, login toSMIC Now or send us a message.